Lines Matching refs:bank
78 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
84 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
109 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,
112 bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction,
118 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,
121 void __iomem *reg = bank->base;
125 reg += bank->regs->set_dataout;
126 bank->context.dataout |= l;
128 reg += bank->regs->clr_dataout;
129 bank->context.dataout &= ~l;
136 static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,
139 bank->context.dataout = omap_gpio_rmw(bank->base + bank->regs->dataout,
143 static inline void omap_gpio_dbck_enable(struct gpio_bank *bank)
145 if (bank->dbck_enable_mask && !bank->dbck_enabled) {
146 clk_enable(bank->dbck);
147 bank->dbck_enabled = true;
149 writel_relaxed(bank->dbck_enable_mask,
150 bank->base + bank->regs->debounce_en);
154 static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)
156 if (bank->dbck_enable_mask && bank->dbck_enabled) {
162 writel_relaxed(0, bank->base + bank->regs->debounce_en);
164 clk_disable(bank->dbck);
165 bank->dbck_enabled = false;
171 * @bank: the gpio bank we're acting upon
172 * @offset: the gpio number on this @bank
181 static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,
188 if (!bank->dbck_flag)
199 clk_enable(bank->dbck);
200 writel_relaxed(debounce, bank->base + bank->regs->debounce);
202 val = omap_gpio_rmw(bank->base + bank->regs->debounce_en, l, enable);
203 bank->dbck_enable_mask = val;
205 clk_disable(bank->dbck);
214 omap_gpio_dbck_enable(bank);
215 if (bank->dbck_enable_mask) {
216 bank->context.debounce = debounce;
217 bank->context.debounce_en = val;
225 * @bank: the gpio bank we're acting upon
226 * @offset: the gpio number on this @bank
229 * this is the only gpio in this bank using debounce, then clear the debounce
231 * if this is the only gpio in the bank using debounce.
233 static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)
237 if (!bank->dbck_flag)
240 if (!(bank->dbck_enable_mask & gpio_bit))
243 bank->dbck_enable_mask &= ~gpio_bit;
244 bank->context.debounce_en &= ~gpio_bit;
245 writel_relaxed(bank->context.debounce_en,
246 bank->base + bank->regs->debounce_en);
248 if (!bank->dbck_enable_mask) {
249 bank->context.debounce = 0;
250 writel_relaxed(bank->context.debounce, bank->base +
251 bank->regs->debounce);
252 clk_disable(bank->dbck);
253 bank->dbck_enabled = false;
258 * Off mode wake-up capable GPIOs in bank(s) that are in the wakeup domain.
260 * in wakeup domain. If bank->non_wakeup_gpios is not configured, assume none
263 static bool omap_gpio_is_off_wakeup_capable(struct gpio_bank *bank, u32 gpio_mask)
265 u32 no_wake = bank->non_wakeup_gpios;
273 static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,
276 void __iomem *base = bank->base;
279 omap_gpio_rmw(base + bank->regs->leveldetect0, gpio_bit,
281 omap_gpio_rmw(base + bank->regs->leveldetect1, gpio_bit,
289 omap_gpio_rmw(base + bank->regs->risingdetect, gpio_bit,
291 omap_gpio_rmw(base + bank->regs->fallingdetect, gpio_bit,
294 bank->context.leveldetect0 =
295 readl_relaxed(bank->base + bank->regs->leveldetect0);
296 bank->context.leveldetect1 =
297 readl_relaxed(bank->base + bank->regs->leveldetect1);
298 bank->context.risingdetect =
299 readl_relaxed(bank->base + bank->regs->risingdetect);
300 bank->context.fallingdetect =
301 readl_relaxed(bank->base + bank->regs->fallingdetect);
303 bank->level_mask = bank->context.leveldetect0 |
304 bank->context.leveldetect1;
307 if (!bank->regs->irqctrl && !omap_gpio_is_off_wakeup_capable(bank, gpio)) {
315 bank->enabled_non_wakeup_gpios |= gpio_bit;
317 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
325 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
327 if (IS_ENABLED(CONFIG_ARCH_OMAP1) && bank->regs->irqctrl) {
328 void __iomem *reg = bank->base + bank->regs->irqctrl;
334 static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,
337 void __iomem *reg = bank->base;
340 if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
341 omap_set_gpio_trigger(bank, gpio, trigger);
342 } else if (bank->regs->irqctrl) {
343 reg += bank->regs->irqctrl;
347 bank->toggle_mask |= BIT(gpio);
356 } else if (bank->regs->edgectrl1) {
358 reg += bank->regs->edgectrl2;
360 reg += bank->regs->edgectrl1;
374 static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)
376 if (bank->regs->pinctrl) {
377 void __iomem *reg = bank->base + bank->regs->pinctrl;
383 if (bank->regs->ctrl && !BANK_USED(bank)) {
384 void __iomem *reg = bank->base + bank->regs->ctrl;
391 bank->context.ctrl = ctrl;
395 static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)
397 if (bank->regs->ctrl && !BANK_USED(bank)) {
398 void __iomem *reg = bank->base + bank->regs->ctrl;
405 bank->context.ctrl = ctrl;
409 static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset)
411 void __iomem *reg = bank->base + bank->regs->direction;
416 static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset)
418 if (!LINE_USED(bank->mod_usage, offset)) {
419 omap_enable_gpio_module(bank, offset);
420 omap_set_gpio_direction(bank, offset, 1);
422 bank->irq_usage |= BIT(offset);
427 struct gpio_bank *bank = omap_irq_data_get_bank(d);
435 if (!bank->regs->leveldetect0 &&
439 raw_spin_lock_irqsave(&bank->lock, flags);
440 retval = omap_set_gpio_triggering(bank, offset, type);
442 raw_spin_unlock_irqrestore(&bank->lock, flags);
445 omap_gpio_init_irq(bank, offset);
446 if (!omap_gpio_is_input(bank, offset)) {
447 raw_spin_unlock_irqrestore(&bank->lock, flags);
451 raw_spin_unlock_irqrestore(&bank->lock, flags);
470 static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
472 void __iomem *reg = bank->base;
474 reg += bank->regs->irqstatus;
478 if (bank->regs->irqstatus2) {
479 reg = bank->base + bank->regs->irqstatus2;
487 static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank,
490 omap_clear_gpio_irqbank(bank, BIT(offset));
493 static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank)
495 void __iomem *reg = bank->base;
497 u32 mask = (BIT(bank->width)) - 1;
499 reg += bank->regs->irqenable;
501 if (bank->regs->irqenable_inv)
507 static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,
510 void __iomem *reg = bank->base;
513 if (bank->regs->set_irqenable && bank->regs->clr_irqenable) {
515 reg += bank->regs->set_irqenable;
516 bank->context.irqenable1 |= gpio_mask;
518 reg += bank->regs->clr_irqenable;
519 bank->context.irqenable1 &= ~gpio_mask;
523 bank->context.irqenable1 =
524 omap_gpio_rmw(reg + bank->regs->irqenable, gpio_mask,
525 enable ^ bank->regs->irqenable_inv);
534 if (bank->regs->wkup_en &&
535 (bank->regs->edgectrl1 || !(bank->non_wakeup_gpios & gpio_mask))) {
536 bank->context.wake_en =
537 omap_gpio_rmw(bank->base + bank->regs->wkup_en,
545 struct gpio_bank *bank = omap_irq_data_get_bank(d);
547 return irq_set_irq_wake(bank->irq, enable);
551 * We need to unmask the GPIO bank interrupt as soon as possible to
552 * avoid missing GPIO interrupts for other lines in the bank.
554 * in the bank to avoid missing nested interrupts for a GPIO line.
555 * If we wait to unmask individual GPIO lines in the bank after the
564 struct gpio_bank *bank = gpiobank;
568 isr_reg = bank->base + bank->regs->irqstatus;
572 if (WARN_ONCE(!pm_runtime_active(bank->chip.parent),
577 raw_spin_lock_irqsave(&bank->lock, lock_flags);
579 enabled = omap_get_gpio_irqbank_mask(bank);
587 edge = isr & ~bank->level_mask;
589 omap_clear_gpio_irqbank(bank, edge);
591 raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
600 raw_spin_lock_irqsave(&bank->lock, lock_flags);
606 * This will be indicated in the bank toggle_mask.
608 if (bank->toggle_mask & (BIT(bit)))
609 omap_toggle_gpio_edge_triggering(bank, bit);
611 raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
613 raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);
615 generic_handle_domain_irq(bank->chip.irq.domain, bit);
617 raw_spin_unlock_irqrestore(&bank->wa_lock,
627 struct gpio_bank *bank = omap_irq_data_get_bank(d);
631 raw_spin_lock_irqsave(&bank->lock, flags);
633 if (!LINE_USED(bank->mod_usage, offset))
634 omap_set_gpio_direction(bank, offset, 1);
635 omap_enable_gpio_module(bank, offset);
636 bank->irq_usage |= BIT(offset);
638 raw_spin_unlock_irqrestore(&bank->lock, flags);
646 struct gpio_bank *bank = omap_irq_data_get_bank(d);
650 raw_spin_lock_irqsave(&bank->lock, flags);
651 bank->irq_usage &= ~(BIT(offset));
652 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
653 omap_clear_gpio_irqstatus(bank, offset);
654 omap_set_gpio_irqenable(bank, offset, 0);
655 if (!LINE_USED(bank->mod_usage, offset))
656 omap_clear_gpio_debounce(bank, offset);
657 omap_disable_gpio_module(bank, offset);
658 raw_spin_unlock_irqrestore(&bank->lock, flags);
663 struct gpio_bank *bank = omap_irq_data_get_bank(data);
665 pm_runtime_get_sync(bank->chip.parent);
670 struct gpio_bank *bank = omap_irq_data_get_bank(data);
672 pm_runtime_put(bank->chip.parent);
677 struct gpio_bank *bank = omap_irq_data_get_bank(d);
681 raw_spin_lock_irqsave(&bank->lock, flags);
682 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
683 omap_set_gpio_irqenable(bank, offset, 0);
684 raw_spin_unlock_irqrestore(&bank->lock, flags);
685 gpiochip_disable_irq(&bank->chip, offset);
690 struct gpio_bank *bank = omap_irq_data_get_bank(d);
695 gpiochip_enable_irq(&bank->chip, offset);
696 raw_spin_lock_irqsave(&bank->lock, flags);
697 omap_set_gpio_irqenable(bank, offset, 1);
704 if (bank->regs->leveldetect0 && bank->regs->wkup_en &&
706 omap_clear_gpio_irqstatus(bank, offset);
709 omap_set_gpio_triggering(bank, offset, trigger);
711 raw_spin_unlock_irqrestore(&bank->lock, flags);
716 struct gpio_bank *bank = omap_irq_data_get_bank(d);
718 seq_printf(p, dev_name(bank->dev));
752 struct gpio_bank *bank = dev_get_drvdata(dev);
753 void __iomem *mask_reg = bank->base +
754 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
757 raw_spin_lock_irqsave(&bank->lock, flags);
758 writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
759 raw_spin_unlock_irqrestore(&bank->lock, flags);
766 struct gpio_bank *bank = dev_get_drvdata(dev);
767 void __iomem *mask_reg = bank->base +
768 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
771 raw_spin_lock_irqsave(&bank->lock, flags);
772 writel_relaxed(bank->context.wake_en, mask_reg);
773 raw_spin_unlock_irqrestore(&bank->lock, flags);
800 static inline void omap_mpuio_init(struct gpio_bank *bank)
802 platform_set_drvdata(&omap_mpuio_device, bank);
812 struct gpio_bank *bank = gpiochip_get_data(chip);
817 raw_spin_lock_irqsave(&bank->lock, flags);
818 omap_enable_gpio_module(bank, offset);
819 bank->mod_usage |= BIT(offset);
820 raw_spin_unlock_irqrestore(&bank->lock, flags);
827 struct gpio_bank *bank = gpiochip_get_data(chip);
830 raw_spin_lock_irqsave(&bank->lock, flags);
831 bank->mod_usage &= ~(BIT(offset));
832 if (!LINE_USED(bank->irq_usage, offset)) {
833 omap_set_gpio_direction(bank, offset, 1);
834 omap_clear_gpio_debounce(bank, offset);
836 omap_disable_gpio_module(bank, offset);
837 raw_spin_unlock_irqrestore(&bank->lock, flags);
844 struct gpio_bank *bank = gpiochip_get_data(chip);
846 if (readl_relaxed(bank->base + bank->regs->direction) & BIT(offset))
854 struct gpio_bank *bank;
857 bank = gpiochip_get_data(chip);
858 raw_spin_lock_irqsave(&bank->lock, flags);
859 omap_set_gpio_direction(bank, offset, 1);
860 raw_spin_unlock_irqrestore(&bank->lock, flags);
866 struct gpio_bank *bank = gpiochip_get_data(chip);
869 if (omap_gpio_is_input(bank, offset))
870 reg = bank->base + bank->regs->datain;
872 reg = bank->base + bank->regs->dataout;
879 struct gpio_bank *bank;
882 bank = gpiochip_get_data(chip);
883 raw_spin_lock_irqsave(&bank->lock, flags);
884 bank->set_dataout(bank, offset, value);
885 omap_set_gpio_direction(bank, offset, 0);
886 raw_spin_unlock_irqrestore(&bank->lock, flags);
893 struct gpio_bank *bank = gpiochip_get_data(chip);
894 void __iomem *base = bank->base;
897 direction = readl_relaxed(base + bank->regs->direction);
901 val |= readl_relaxed(base + bank->regs->datain) & m;
905 val |= readl_relaxed(base + bank->regs->dataout) & m;
915 struct gpio_bank *bank;
919 bank = gpiochip_get_data(chip);
921 raw_spin_lock_irqsave(&bank->lock, flags);
922 ret = omap2_set_gpio_debounce(bank, offset, debounce);
923 raw_spin_unlock_irqrestore(&bank->lock, flags);
958 struct gpio_bank *bank;
961 bank = gpiochip_get_data(chip);
962 raw_spin_lock_irqsave(&bank->lock, flags);
963 bank->set_dataout(bank, offset, value);
964 raw_spin_unlock_irqrestore(&bank->lock, flags);
970 struct gpio_bank *bank = gpiochip_get_data(chip);
971 void __iomem *reg = bank->base + bank->regs->dataout;
975 raw_spin_lock_irqsave(&bank->lock, flags);
978 bank->context.dataout = l;
979 raw_spin_unlock_irqrestore(&bank->lock, flags);
984 static void omap_gpio_show_rev(struct gpio_bank *bank)
989 if (called || bank->regs->revision == USHRT_MAX)
992 rev = readw_relaxed(bank->base + bank->regs->revision);
999 static void omap_gpio_mod_init(struct gpio_bank *bank)
1001 void __iomem *base = bank->base;
1004 if (bank->width == 16)
1007 if (bank->is_mpuio) {
1008 writel_relaxed(l, bank->base + bank->regs->irqenable);
1012 omap_gpio_rmw(base + bank->regs->irqenable, l,
1013 bank->regs->irqenable_inv);
1014 omap_gpio_rmw(base + bank->regs->irqstatus, l,
1015 !bank->regs->irqenable_inv);
1016 if (bank->regs->debounce_en)
1017 writel_relaxed(0, base + bank->regs->debounce_en);
1020 bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);
1022 if (bank->regs->ctrl)
1023 writel_relaxed(0, base + bank->regs->ctrl);
1026 static int omap_gpio_chip_init(struct gpio_bank *bank, struct device *pm_dev)
1037 bank->chip.request = omap_gpio_request;
1038 bank->chip.free = omap_gpio_free;
1039 bank->chip.get_direction = omap_gpio_get_direction;
1040 bank->chip.direction_input = omap_gpio_input;
1041 bank->chip.get = omap_gpio_get;
1042 bank->chip.get_multiple = omap_gpio_get_multiple;
1043 bank->chip.direction_output = omap_gpio_output;
1044 bank->chip.set_config = omap_gpio_set_config;
1045 bank->chip.set = omap_gpio_set;
1046 bank->chip.set_multiple = omap_gpio_set_multiple;
1047 if (bank->is_mpuio) {
1048 bank->chip.label = "mpuio";
1049 if (bank->regs->wkup_en)
1050 bank->chip.parent = &omap_mpuio_device.dev;
1052 label = devm_kasprintf(bank->chip.parent, GFP_KERNEL, "gpio-%d-%d",
1053 gpio, gpio + bank->width - 1);
1056 bank->chip.label = label;
1058 bank->chip.base = -1;
1059 bank->chip.ngpio = bank->width;
1061 irq = &bank->chip.irq;
1063 if (bank->is_mpuio && !bank->regs->wkup_en)
1070 irq->parents = &bank->irq;
1072 ret = gpiochip_add_data(&bank->chip, bank);
1074 return dev_err_probe(bank->chip.parent, ret, "Could not register gpio chip\n");
1076 irq_domain_set_pm_device(bank->chip.irq.domain, pm_dev);
1077 ret = devm_request_irq(bank->chip.parent, bank->irq,
1079 0, dev_name(bank->chip.parent), bank);
1081 gpiochip_remove(&bank->chip);
1083 if (!bank->is_mpuio)
1084 gpio += bank->width;
1109 static void omap_gpio_restore_context(struct gpio_bank *bank)
1111 const struct omap_gpio_reg_offs *regs = bank->regs;
1112 void __iomem *base = bank->base;
1114 writel_relaxed(bank->context.sysconfig, base + regs->sysconfig);
1115 writel_relaxed(bank->context.wake_en, base + regs->wkup_en);
1116 writel_relaxed(bank->context.ctrl, base + regs->ctrl);
1117 writel_relaxed(bank->context.leveldetect0, base + regs->leveldetect0);
1118 writel_relaxed(bank->context.leveldetect1, base + regs->leveldetect1);
1119 writel_relaxed(bank->context.risingdetect, base + regs->risingdetect);
1120 writel_relaxed(bank->context.fallingdetect, base + regs->fallingdetect);
1121 writel_relaxed(bank->context.dataout, base + regs->dataout);
1122 writel_relaxed(bank->context.oe, base + regs->direction);
1124 if (bank->dbck_enable_mask) {
1125 writel_relaxed(bank->context.debounce, base + regs->debounce);
1126 writel_relaxed(bank->context.debounce_en,
1130 writel_relaxed(bank->context.irqenable1, base + regs->irqenable);
1131 writel_relaxed(bank->context.irqenable2, base + regs->irqenable2);
1134 static void omap_gpio_idle(struct gpio_bank *bank, bool may_lose_context)
1136 struct device *dev = bank->chip.parent;
1137 void __iomem *base = bank->base;
1140 bank->saved_datain = readl_relaxed(base + bank->regs->datain);
1143 if (bank->loses_context)
1144 bank->context.sysconfig = readl_relaxed(base + bank->regs->sysconfig);
1146 if (!bank->enabled_non_wakeup_gpios)
1150 mask = bank->enabled_non_wakeup_gpios & bank->context.fallingdetect;
1151 mask &= ~bank->context.risingdetect;
1152 bank->saved_datain |= mask;
1155 mask = bank->enabled_non_wakeup_gpios & bank->context.risingdetect;
1156 mask &= ~bank->context.fallingdetect;
1157 bank->saved_datain &= ~mask;
1167 if (!bank->loses_context && bank->enabled_non_wakeup_gpios) {
1168 nowake = bank->enabled_non_wakeup_gpios;
1169 omap_gpio_rmw(base + bank->regs->fallingdetect, nowake, ~nowake);
1170 omap_gpio_rmw(base + bank->regs->risingdetect, nowake, ~nowake);
1174 if (bank->get_context_loss_count)
1175 bank->context_loss_count =
1176 bank->get_context_loss_count(dev);
1178 omap_gpio_dbck_disable(bank);
1181 static void omap_gpio_unidle(struct gpio_bank *bank)
1183 struct device *dev = bank->chip.parent;
1192 if (bank->loses_context && !bank->context_valid) {
1193 omap_gpio_init_context(bank);
1195 if (bank->get_context_loss_count)
1196 bank->context_loss_count =
1197 bank->get_context_loss_count(dev);
1200 omap_gpio_dbck_enable(bank);
1202 if (bank->loses_context) {
1203 if (!bank->get_context_loss_count) {
1204 omap_gpio_restore_context(bank);
1206 c = bank->get_context_loss_count(dev);
1207 if (c != bank->context_loss_count) {
1208 omap_gpio_restore_context(bank);
1215 writel_relaxed(bank->context.fallingdetect,
1216 bank->base + bank->regs->fallingdetect);
1217 writel_relaxed(bank->context.risingdetect,
1218 bank->base + bank->regs->risingdetect);
1221 l = readl_relaxed(bank->base + bank->regs->datain);
1229 l ^= bank->saved_datain;
1230 l &= bank->enabled_non_wakeup_gpios;
1236 gen0 = l & bank->context.fallingdetect;
1237 gen0 &= bank->saved_datain;
1239 gen1 = l & bank->context.risingdetect;
1240 gen1 &= ~(bank->saved_datain);
1243 gen = l & (~(bank->context.fallingdetect) &
1244 ~(bank->context.risingdetect));
1251 old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);
1252 old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);
1254 if (!bank->regs->irqstatus_raw0) {
1255 writel_relaxed(old0 | gen, bank->base +
1256 bank->regs->leveldetect0);
1257 writel_relaxed(old1 | gen, bank->base +
1258 bank->regs->leveldetect1);
1261 if (bank->regs->irqstatus_raw0) {
1262 writel_relaxed(old0 | l, bank->base +
1263 bank->regs->leveldetect0);
1264 writel_relaxed(old1 | l, bank->base +
1265 bank->regs->leveldetect1);
1267 writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
1268 writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
1275 struct gpio_bank *bank;
1280 bank = container_of(nb, struct gpio_bank, nb);
1282 raw_spin_lock_irqsave(&bank->lock, flags);
1283 if (bank->is_suspended)
1288 mask = omap_get_gpio_irqbank_mask(bank);
1289 isr = readl_relaxed(bank->base + bank->regs->irqstatus) & mask;
1294 omap_gpio_idle(bank, true);
1298 omap_gpio_unidle(bank);
1303 raw_spin_unlock_irqrestore(&bank->lock, flags);
1398 struct gpio_bank *bank;
1407 bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
1408 if (!bank)
1411 bank->dev = dev;
1413 bank->irq = platform_get_irq(pdev, 0);
1414 if (bank->irq < 0)
1415 return bank->irq;
1417 bank->chip.parent = dev;
1418 bank->chip.owner = THIS_MODULE;
1419 bank->dbck_flag = pdata->dbck_flag;
1420 bank->stride = pdata->bank_stride;
1421 bank->width = pdata->bank_width;
1422 bank->is_mpuio = pdata->is_mpuio;
1423 bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1424 bank->regs = pdata->regs;
1428 bank->loses_context = true;
1430 bank->loses_context = pdata->loses_context;
1432 if (bank->loses_context)
1433 bank->get_context_loss_count =
1437 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1438 bank->set_dataout = omap_set_gpio_dataout_reg;
1440 bank->set_dataout = omap_set_gpio_dataout_mask;
1442 raw_spin_lock_init(&bank->lock);
1443 raw_spin_lock_init(&bank->wa_lock);
1446 bank->base = devm_platform_ioremap_resource(pdev, 0);
1447 if (IS_ERR(bank->base)) {
1448 return PTR_ERR(bank->base);
1451 if (bank->dbck_flag) {
1452 bank->dbck = devm_clk_get(dev, "dbclk");
1453 if (IS_ERR(bank->dbck)) {
1456 bank->dbck_flag = false;
1458 clk_prepare(bank->dbck);
1462 platform_set_drvdata(pdev, bank);
1467 if (bank->is_mpuio)
1468 omap_mpuio_init(bank);
1470 omap_gpio_mod_init(bank);
1472 ret = omap_gpio_chip_init(bank, dev);
1476 if (bank->dbck_flag)
1477 clk_unprepare(bank->dbck);
1481 omap_gpio_show_rev(bank);
1483 bank->nb.notifier_call = gpio_omap_cpu_notifier;
1484 cpu_pm_register_notifier(&bank->nb);
1493 struct gpio_bank *bank = platform_get_drvdata(pdev);
1495 cpu_pm_unregister_notifier(&bank->nb);
1496 gpiochip_remove(&bank->chip);
1498 if (bank->dbck_flag)
1499 clk_unprepare(bank->dbck);
1504 struct gpio_bank *bank = dev_get_drvdata(dev);
1507 raw_spin_lock_irqsave(&bank->lock, flags);
1508 omap_gpio_idle(bank, true);
1509 bank->is_suspended = true;
1510 raw_spin_unlock_irqrestore(&bank->lock, flags);
1517 struct gpio_bank *bank = dev_get_drvdata(dev);
1520 raw_spin_lock_irqsave(&bank->lock, flags);
1521 omap_gpio_unidle(bank);
1522 bank->is_suspended = false;
1523 raw_spin_unlock_irqrestore(&bank->lock, flags);
1530 struct gpio_bank *bank = dev_get_drvdata(dev);
1532 if (bank->is_suspended)
1535 bank->needs_resume = 1;
1542 struct gpio_bank *bank = dev_get_drvdata(dev);
1544 if (!bank->needs_resume)
1547 bank->needs_resume = 0;