drivers/gpio/gpio-mlxbf.c

52 	struct mlxbf_gpio_state *gs;
57 	gs = devm_kzalloc(&pdev->dev, sizeof(*gs), GFP_KERNEL);
58 	if (!gs)
61 	gs->base = devm_platform_ioremap_resource(pdev, 0);
62 	if (IS_ERR(gs->base))
63 		return PTR_ERR(gs->base);
65 	gc = &gs->gc;
67 			 gs->base + MLXBF_GPIO_PIN_STATE,
70 			 gs->base + MLXBF_GPIO_PIN_DIR_O,
71 			 gs->base + MLXBF_GPIO_PIN_DIR_I,
79 	ret = devm_gpiochip_add_data(dev, &gs->gc, gs);
85 	platform_set_drvdata(pdev, gs);
93 	struct mlxbf_gpio_state *gs = platform_get_drvdata(pdev);
95 	gs->csave_regs.scratchpad = readq(gs->base + MLXBF_GPIO_SCRATCHPAD);
96 	gs->csave_regs.pad_control[0] =
97 		readq(gs->base + MLXBF_GPIO_PAD_CONTROL_FIRST_WORD);
98 	gs->csave_regs.pad_control[1] =
99 		readq(gs->base + MLXBF_GPIO_PAD_CONTROL_1_FIRST_WORD);
100 	gs->csave_regs.pad_control[2] =
101 		readq(gs->base + MLXBF_GPIO_PAD_CONTROL_2_FIRST_WORD);
102 	gs->csave_regs.pad_control[3] =
103 		readq(gs->base + MLXBF_GPIO_PAD_CONTROL_3_FIRST_WORD);
104 	gs->csave_regs.pin_dir_i = readq(gs->base + MLXBF_GPIO_PIN_DIR_I);
105 	gs->csave_regs.pin_dir_o = readq(gs->base + MLXBF_GPIO_PIN_DIR_O);
112 	struct mlxbf_gpio_state *gs = platform_get_drvdata(pdev);
114 	writeq(gs->csave_regs.scratchpad, gs->base + MLXBF_GPIO_SCRATCHPAD);
115 	writeq(gs->csave_regs.pad_control[0],
116 	       gs->base + MLXBF_GPIO_PAD_CONTROL_FIRST_WORD);
117 	writeq(gs->csave_regs.pad_control[1],
118 	       gs->base + MLXBF_GPIO_PAD_CONTROL_1_FIRST_WORD);
119 	writeq(gs->csave_regs.pad_control[2],
120 	       gs->base + MLXBF_GPIO_PAD_CONTROL_2_FIRST_WORD);
121 	writeq(gs->csave_regs.pad_control[3],
122 	       gs->base + MLXBF_GPIO_PAD_CONTROL_3_FIRST_WORD);
123 	writeq(gs->csave_regs.pin_dir_i, gs->base + MLXBF_GPIO_PIN_DIR_I);
124 	writeq(gs->csave_regs.pin_dir_o, gs->base + MLXBF_GPIO_PIN_DIR_O);