drivers/gpio/gpio-brcmstb.c

26 #define GIO_BANK_OFF(bank, off)	(((bank) * GIO_BANK_SIZE) + (off * sizeof(u32)))
27 #define GIO_ODEN(bank)          GIO_BANK_OFF(bank, GIO_REG_ODEN)
28 #define GIO_DATA(bank)          GIO_BANK_OFF(bank, GIO_REG_DATA)
29 #define GIO_IODIR(bank)         GIO_BANK_OFF(bank, GIO_REG_IODIR)
30 #define GIO_EC(bank)            GIO_BANK_OFF(bank, GIO_REG_EC)
31 #define GIO_EI(bank)            GIO_BANK_OFF(bank, GIO_REG_EI)
32 #define GIO_MASK(bank)          GIO_BANK_OFF(bank, GIO_REG_MASK)
33 #define GIO_LEVEL(bank)         GIO_BANK_OFF(bank, GIO_REG_LEVEL)
34 #define GIO_STAT(bank)          GIO_BANK_OFF(bank, GIO_REG_STAT)
66 	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
67 	return bank->parent_priv;
71 __brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
73 	void __iomem *reg_base = bank->parent_priv->reg_base;
75 	return bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) &
76 	       bank->gc.read_reg(reg_base + GIO_MASK(bank->id));
80 brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
85 	raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
86 	status = __brcmstb_gpio_get_active_irqs(bank);
87 	raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
93 					struct brcmstb_gpio_bank *bank)
95 	return hwirq - (bank->gc.base - bank->parent_priv->gpio_base);
98 static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank,
101 	struct gpio_chip *gc = &bank->gc;
102 	struct brcmstb_gpio_priv *priv = bank->parent_priv;
103 	u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(hwirq, bank));
108 	imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id));
113 	gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask);
133 	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
135 	brcmstb_gpio_set_imask(bank, d->hwirq, false);
141 	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
143 	brcmstb_gpio_set_imask(bank, d->hwirq, true);
149 	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
150 	struct brcmstb_gpio_priv *priv = bank->parent_priv;
151 	u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
153 	gc->write_reg(priv->reg_base + GIO_STAT(bank->id), mask);
159 	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
160 	struct brcmstb_gpio_priv *priv = bank->parent_priv;
161 	u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
197 	raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
199 	iedge_config = bank->gc.read_reg(priv->reg_base +
200 			GIO_EC(bank->id)) & ~mask;
201 	iedge_insensitive = bank->gc.read_reg(priv->reg_base +
202 			GIO_EI(bank->id)) & ~mask;
203 	ilevel = bank->gc.read_reg(priv->reg_base +
204 			GIO_LEVEL(bank->id)) & ~mask;
206 	bank->gc.write_reg(priv->reg_base + GIO_EC(bank->id),
208 	bank->gc.write_reg(priv->reg_base + GIO_EI(bank->id),
210 	bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id),
213 	raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
235 	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
236 	struct brcmstb_gpio_priv *priv = bank->parent_priv;
237 	u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
244 		bank->wake_active |= mask;
246 		bank->wake_active &= ~mask;
262 static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank)
264 	struct brcmstb_gpio_priv *priv = bank->parent_priv;
266 	int hwbase = bank->gc.base - priv->gpio_base;
269 	while ((status = brcmstb_gpio_get_active_irqs(bank))) {
273 			if (offset >= bank->width)
275 					 "IRQ for invalid GPIO (bank=%d, offset=%d)\n",
276 					 bank->id, offset);
287 	struct brcmstb_gpio_bank *bank;
293 	list_for_each_entry(bank, &priv->bank_list, node)
294 		brcmstb_gpio_irq_bank_handler(bank);
301 	struct brcmstb_gpio_bank *bank;
305 	list_for_each_entry_reverse(bank, &priv->bank_list, node) {
306 		i += bank->gc.ngpio;
308 			return bank;
325 	struct brcmstb_gpio_bank *bank =
330 	if (!bank)
333 	dev_dbg(&pdev->dev, "Mapping irq %d for gpio line %d (bank %d)\n",
334 		irq, (int)hwirq, bank->id);
335 	ret = irq_set_chip_data(irq, &bank->gc);
363 		of_property_count_u32_elems(np, "brcm,gpio-bank-widths");
366 		dev_err(dev, "Mismatch in banks: res had %d, bank-widths had %d\n",
377 	struct brcmstb_gpio_bank *bank;
396 	list_for_each_entry(bank, &priv->bank_list, node)
397 		gpiochip_remove(&bank->gc);
404 	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
419 	if (unlikely(offset >= bank->width)) {
496 				   struct brcmstb_gpio_bank *bank)
498 	struct gpio_chip *gc = &bank->gc;
502 		bank->saved_regs[i] = gc->read_reg(priv->reg_base +
503 						   GIO_BANK_OFF(bank->id, i));
509 	struct brcmstb_gpio_bank *bank;
517 	list_for_each_entry(bank, &priv->bank_list, node) {
518 		gc = &bank->gc;
521 			brcmstb_gpio_bank_save(priv, bank);
525 			imask = bank->wake_active;
528 		gc->write_reg(priv->reg_base + GIO_MASK(bank->id),
541 				      struct brcmstb_gpio_bank *bank)
543 	struct gpio_chip *gc = &bank->gc;
547 		gc->write_reg(priv->reg_base + GIO_BANK_OFF(bank->id, i),
548 			      bank->saved_regs[i]);
560 	struct brcmstb_gpio_bank *bank;
563 	list_for_each_entry(bank, &priv->bank_list, node) {
564 		need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
565 		brcmstb_gpio_bank_restore(priv, bank);
641 	of_property_for_each_u32(np, "brcm,gpio-bank-widths", prop, p,
643 		struct brcmstb_gpio_bank *bank;
647 		 * If bank_width is 0, then there is an empty bank in the
651 			dev_dbg(dev, "Width 0 found: Empty bank @ %d\n",
658 		bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
659 		if (!bank) {
664 		bank->parent_priv = priv;
665 		bank->id = num_banks;
667 			dev_err(dev, "Invalid bank width %d\n", bank_width);
671 			bank->width = bank_width;
678 		gc = &bank->gc;
680 				reg_base + GIO_DATA(bank->id),
682 				reg_base + GIO_IODIR(bank->id), flags);
697 		/* not all ngpio lines are valid, will use bank width later */
699 		gc->offset = bank->id * MAX_GPIO_PER_BANK;
707 		need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
708 		gc->write_reg(reg_base + GIO_MASK(bank->id), 0);
710 		err = gpiochip_add_data(gc, bank);
712 			dev_err(dev, "Could not add gpiochip for bank %d\n",
713 					bank->id);
718 		dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id,
719 			gc->base, gc->ngpio, bank->width);
721 		/* Everything looks good, so add bank to list */
722 		list_add(&bank->node, &priv->bank_list);