drivers/gpio/gpio-brcmstb.c

26 #define GIO_BANK_OFF(bank, off)	(((bank) * GIO_BANK_SIZE) + (off * sizeof(u32)))
27 #define GIO_ODEN(bank)          GIO_BANK_OFF(bank, GIO_REG_ODEN)
28 #define GIO_DATA(bank)          GIO_BANK_OFF(bank, GIO_REG_DATA)
29 #define GIO_IODIR(bank)         GIO_BANK_OFF(bank, GIO_REG_IODIR)
30 #define GIO_EC(bank)            GIO_BANK_OFF(bank, GIO_REG_EC)
31 #define GIO_EI(bank)            GIO_BANK_OFF(bank, GIO_REG_EI)
32 #define GIO_MASK(bank)          GIO_BANK_OFF(bank, GIO_REG_MASK)
33 #define GIO_LEVEL(bank)         GIO_BANK_OFF(bank, GIO_REG_LEVEL)
34 #define GIO_STAT(bank)          GIO_BANK_OFF(bank, GIO_REG_STAT)
65 	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
66 	return bank->parent_priv;
70 __brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
72 	void __iomem *reg_base = bank->parent_priv->reg_base;
74 	return bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) &
75 	       bank->gc.read_reg(reg_base + GIO_MASK(bank->id));
79 brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
84 	raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
85 	status = __brcmstb_gpio_get_active_irqs(bank);
86 	raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
92 					struct brcmstb_gpio_bank *bank)
94 	return hwirq - bank->gc.offset;
97 static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank,
100 	struct gpio_chip *gc = &bank->gc;
101 	struct brcmstb_gpio_priv *priv = bank->parent_priv;
102 	u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(hwirq, bank));
107 	imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id));
112 	gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask);
132 	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
134 	brcmstb_gpio_set_imask(bank, d->hwirq, false);
140 	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
142 	brcmstb_gpio_set_imask(bank, d->hwirq, true);
148 	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
149 	struct brcmstb_gpio_priv *priv = bank->parent_priv;
150 	u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
152 	gc->write_reg(priv->reg_base + GIO_STAT(bank->id), mask);
158 	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
159 	struct brcmstb_gpio_priv *priv = bank->parent_priv;
160 	u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
196 	raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
198 	iedge_config = bank->gc.read_reg(priv->reg_base +
199 			GIO_EC(bank->id)) & ~mask;
200 	iedge_insensitive = bank->gc.read_reg(priv->reg_base +
201 			GIO_EI(bank->id)) & ~mask;
202 	ilevel = bank->gc.read_reg(priv->reg_base +
203 			GIO_LEVEL(bank->id)) & ~mask;
205 	bank->gc.write_reg(priv->reg_base + GIO_EC(bank->id),
207 	bank->gc.write_reg(priv->reg_base + GIO_EI(bank->id),
209 	bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id),
212 	raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
234 	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
235 	struct brcmstb_gpio_priv *priv = bank->parent_priv;
236 	u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
243 		bank->wake_active |= mask;
245 		bank->wake_active &= ~mask;
261 static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank)
263 	struct brcmstb_gpio_priv *priv = bank->parent_priv;
265 	int hwbase = bank->gc.offset;
268 	while ((status = brcmstb_gpio_get_active_irqs(bank))) {
272 			if (offset >= bank->width)
274 					 "IRQ for invalid GPIO (bank=%d, offset=%d)\n",
275 					 bank->id, offset);
286 	struct brcmstb_gpio_bank *bank;
292 	list_for_each_entry(bank, &priv->bank_list, node)
293 		brcmstb_gpio_irq_bank_handler(bank);
300 	struct brcmstb_gpio_bank *bank;
304 	list_for_each_entry_reverse(bank, &priv->bank_list, node) {
305 		i += bank->gc.ngpio;
307 			return bank;
324 	struct brcmstb_gpio_bank *bank =
329 	if (!bank)
332 	dev_dbg(&pdev->dev, "Mapping irq %d for gpio line %d (bank %d)\n",
333 		irq, (int)hwirq, bank->id);
334 	ret = irq_set_chip_data(irq, &bank->gc);
362 		of_property_count_u32_elems(np, "brcm,gpio-bank-widths");
365 		dev_err(dev, "Mismatch in banks: res had %d, bank-widths had %d\n",
376 	struct brcmstb_gpio_bank *bank;
395 	list_for_each_entry(bank, &priv->bank_list, node)
396 		gpiochip_remove(&bank->gc);
403 	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
414 	offset = gpiospec->args[0] - bank->gc.offset;
418 	if (unlikely(offset >= bank->width)) {
495 				   struct brcmstb_gpio_bank *bank)
497 	struct gpio_chip *gc = &bank->gc;
501 		bank->saved_regs[i] = gc->read_reg(priv->reg_base +
502 						   GIO_BANK_OFF(bank->id, i));
508 	struct brcmstb_gpio_bank *bank;
516 	list_for_each_entry(bank, &priv->bank_list, node) {
517 		gc = &bank->gc;
520 			brcmstb_gpio_bank_save(priv, bank);
524 			imask = bank->wake_active;
527 		gc->write_reg(priv->reg_base + GIO_MASK(bank->id),
540 				      struct brcmstb_gpio_bank *bank)
542 	struct gpio_chip *gc = &bank->gc;
546 		gc->write_reg(priv->reg_base + GIO_BANK_OFF(bank->id, i),
547 			      bank->saved_regs[i]);
559 	struct brcmstb_gpio_bank *bank;
562 	list_for_each_entry(bank, &priv->bank_list, node) {
563 		need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
564 		brcmstb_gpio_bank_restore(priv, bank);
639 	of_property_for_each_u32(np, "brcm,gpio-bank-widths", prop, p,
641 		struct brcmstb_gpio_bank *bank;
645 		 * If bank_width is 0, then there is an empty bank in the
649 			dev_dbg(dev, "Width 0 found: Empty bank @ %d\n",
656 		bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
657 		if (!bank) {
662 		bank->parent_priv = priv;
663 		bank->id = num_banks;
665 			dev_err(dev, "Invalid bank width %d\n", bank_width);
669 			bank->width = bank_width;
676 		gc = &bank->gc;
678 				reg_base + GIO_DATA(bank->id),
680 				reg_base + GIO_IODIR(bank->id), flags);
694 		/* not all ngpio lines are valid, will use bank width later */
696 		gc->offset = bank->id * MAX_GPIO_PER_BANK;
706 		need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
707 		gc->write_reg(reg_base + GIO_MASK(bank->id), 0);
709 		err = gpiochip_add_data(gc, bank);
711 			dev_err(dev, "Could not add gpiochip for bank %d\n",
712 					bank->id);
717 		dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id,
718 			gc->base, gc->ngpio, bank->width);
720 		/* Everything looks good, so add bank to list */
721 		list_add(&bank->node, &priv->bank_list);