drivers/gpio/gpio-bcm-kona.c

61 	void __iomem *reg_base;
76 static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base,
79 	writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET);
80 	writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id));
92 	val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
94 	bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
108 	val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
110 	bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
118 	void __iomem *reg_base = kona_gpio->reg_base;
121 	val = readl(reg_base + GPIO_CONTROL(gpio)) & GPIO_GPCTR0_IOTR_MASK;
128 	void __iomem *reg_base;
135 	reg_base = kona_gpio->reg_base;
144 	val = readl(reg_base + reg_offset);
146 	writel(val, reg_base + reg_offset);
155 	void __iomem *reg_base;
162 	reg_base = kona_gpio->reg_base;
171 	val = readl(reg_base + reg_offset);
197 	void __iomem *reg_base;
202 	reg_base = kona_gpio->reg_base;
205 	val = readl(reg_base + GPIO_CONTROL(gpio));
208 	writel(val, reg_base + GPIO_CONTROL(gpio));
219 	void __iomem *reg_base;
226 	reg_base = kona_gpio->reg_base;
229 	val = readl(reg_base + GPIO_CONTROL(gpio));
232 	writel(val, reg_base + GPIO_CONTROL(gpio));
235 	val = readl(reg_base + reg_offset);
237 	writel(val, reg_base + reg_offset);
258 	void __iomem *reg_base;
263 	reg_base = kona_gpio->reg_base;
285 	val = readl(reg_base + GPIO_CONTROL(gpio));
296 	writel(val, reg_base + GPIO_CONTROL(gpio));
333 	void __iomem *reg_base;
341 	reg_base = kona_gpio->reg_base;
344 	val = readl(reg_base + GPIO_INT_STATUS(bank_id));
346 	writel(val, reg_base + GPIO_INT_STATUS(bank_id));
354 	void __iomem *reg_base;
362 	reg_base = kona_gpio->reg_base;
365 	val = readl(reg_base + GPIO_INT_MASK(bank_id));
367 	writel(val, reg_base + GPIO_INT_MASK(bank_id));
376 	void __iomem *reg_base;
384 	reg_base = kona_gpio->reg_base;
387 	val = readl(reg_base + GPIO_INT_MSKCLR(bank_id));
389 	writel(val, reg_base + GPIO_INT_MSKCLR(bank_id));
398 	void __iomem *reg_base;
405 	reg_base = kona_gpio->reg_base;
430 	val = readl(reg_base + GPIO_CONTROL(gpio));
433 	writel(val, reg_base + GPIO_CONTROL(gpio));
442 	void __iomem *reg_base;
455 	reg_base = bank->kona_gpio->reg_base;
458 	while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) &
459 		    (~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) {
466 			writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) |
467 			       BIT(bit), reg_base + GPIO_INT_STATUS(bank_id));
542 	void __iomem *reg_base;
545 	reg_base = kona_gpio->reg_base;
549 		bcm_kona_gpio_write_lock_regs(reg_base, i, UNLOCK_CODE);
550 		writel(0xffffffff, reg_base + GPIO_INT_MASK(i));
551 		writel(0xffffffff, reg_base + GPIO_INT_STATUS(i));
553 		bcm_kona_gpio_write_lock_regs(reg_base, i, LOCK_CODE);
605 	kona_gpio->reg_base = devm_platform_ioremap_resource(pdev, 0);
606 	if (IS_ERR(kona_gpio->reg_base)) {
607 		ret = PTR_ERR(kona_gpio->reg_base);