Lines Matching refs:baseaddr
302 * @baseaddr: Base address of the DDR controller.
317 void __iomem *baseaddr;
362 base = priv->baseaddr;
418 base = priv->baseaddr;
531 priv->baseaddr + DDR_QOS_IRQ_EN_OFST);
539 priv->baseaddr + ECC_CLR_OFST);
551 priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
558 writel(0, priv->baseaddr + ECC_CLR_OFST);
585 regval = readl(priv->baseaddr + DDR_QOS_IRQ_STAT_OFST);
603 writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST);
839 dimm->mtype = p_data->get_mtype(priv->baseaddr);
842 dimm->dtype = p_data->get_dtype(priv->baseaddr);
1020 writel(regval, priv->baseaddr + ECC_POISON0_OFST);
1025 writel(regval, priv->baseaddr + ECC_POISON1_OFST);
1037 readl(priv->baseaddr + ECC_POISON0_OFST),
1038 readl(priv->baseaddr + ECC_POISON1_OFST),
1065 (((readl(priv->baseaddr + ECC_CFG1_OFST)) & 0x3) == 0x3)
1076 writel(0, priv->baseaddr + DDRC_SWCTL);
1078 writel(ECC_CEPOISON_MASK, priv->baseaddr + ECC_CFG1_OFST);
1080 writel(ECC_UEPOISON_MASK, priv->baseaddr + ECC_CFG1_OFST);
1081 writel(1, priv->baseaddr + DDRC_SWCTL);
1172 memtype = readl(priv->baseaddr + CTRL_OFST);
1319 addrmap[index] = readl(priv->baseaddr + addrmap_offset);
1349 void __iomem *baseaddr;
1352 baseaddr = devm_platform_ioremap_resource(pdev, 0);
1353 if (IS_ERR(baseaddr))
1354 return PTR_ERR(baseaddr);
1360 if (!p_data->get_ecc_state(baseaddr)) {
1381 priv->baseaddr = baseaddr;
1419 writel(0x0, baseaddr + ECC_CTRL_OFST);