Lines Matching defs:width
142 /* DDR Control Register width definitions */
636 * zynq_get_dtype - Return the controller memory width.
639 * Get the EDAC device type width appropriate for the current controller
642 * Return: a device type width enumeration.
647 u32 width;
649 width = readl(base + CTRL_OFST);
650 width = (width & CTRL_BW_MASK) >> CTRL_BW_SHIFT;
652 switch (width) {
667 * zynqmp_get_dtype - Return the controller memory width.
670 * Get the EDAC device type width appropriate for the current controller
673 * Return: a device type width enumeration.
678 u32 width;
680 width = readl(base + CTRL_OFST);
681 width = (width & ECC_CTRL_BUSWIDTH_MASK) >> ECC_CTRL_BUSWIDTH_SHIFT;
682 switch (width) {
1169 u32 width, memtype;
1173 width = (memtype & ECC_CTRL_BUSWIDTH_MASK) >> ECC_CTRL_BUSWIDTH_SHIFT;
1198 if (width == DDRCTL_EWDTH_64) {
1218 } else if (width == DDRCTL_EWDTH_32) {
1264 if (width) {
1265 for (index = 9; index > width; index--) {
1266 priv->col_shift[index] = priv->col_shift[index - width];
1267 priv->col_shift[index - width] = 0;