drivers/edac/sb_edac.c

363 	u8			bus, mc;
587 #define knl_channel_remap(mc, chan) ((mc) ? (chan) : (chan) + 3)
1143  * @mc:		which memory controller (0 or 1)
1154 		const int mc,
1163 	switch (mc) {
1244  * entry 0: mc 0:2   channel 18:19
1245  *       1: mc 3:5   channel 20:21
1246  *       2: mc 6:8   channel 22:23
1247  *       3: mc 9:11  channel 24:25
1248  *       4: mc 12:14 channel 26:27
1249  *       5: mc 15:17 channel 28:29
1258 	int mc, chan;
1262 	mc = GET_BITFIELD(reg, entry*3, (entry*3)+2);
1265 	return knl_channel_remap(mc, chan);
1355 	u64 sad_actual_size[2]; /* sad size accounting for holes, per mc */
1363 	int mc;
1405 				edac_dbg(0, "mc route table for CHA %d: %s\n",
1408 				edac_dbg(0, "mc route table for CHA %d-%d: %s\n",
1415 		edac_dbg(0, "mc route table for CHA %d: %s\n",
1418 		edac_dbg(0, "mc route table for CHA %d-%d: %s\n",
1483 		for (mc = 0; mc < 2; mc++) {
1484 			sad_actual_size[mc] = 0;
1492 						mc,
1514 							mc);
1515 						sad_actual_size[mc] += tad_size;
1521 		for (mc = 0; mc < 2; mc++) {
1523 				mc, sad_actual_size[mc], sad_actual_size[mc]);
1554 			mc = knl_channel_mc(channel);
1556 				edac_dbg(4, "mc channel %d contributes %lld bytes via sad entry %d\n",
1558 					sad_actual_size[mc]/intrlv_ways,
1561 					sad_actual_size[mc]/intrlv_ways;
1662 				edac_dbg(0, "mc#%d: ha %d channel %d, dimm %d, %lld MiB (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n",
1663 					 pvt->sbridge_dev->mc, pvt->sbridge_dev->dom, i, j,
1695 	edac_dbg(0, "mc#%d: Node ID: %d, source ID: %d\n",
1696 		 pvt->sbridge_dev->mc,
2110 		edac_dbg(0, "mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n",
2111 			 pvt->sbridge_dev->mc,
3164 			 * back to mc. To figure out mc we check machine check
3363 	mci = edac_mc_alloc(sbridge_dev->mc, ARRAY_SIZE(layers), layers,
3571 	u8 mc, num_mc = 0;
3583 	mc = 0;
3587 			 mc, mc + 1, num_mc);
3589 		sbridge_dev->mc = mc++;