drivers/edac/qcom_edac.c

92 	int ret;
98 	ret = regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->cmn_interrupt_2_enable,
101 	if (ret)
102 		return ret;
104 	ret = regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->trp_interrupt_0_enable,
107 	if (ret)
108 		return ret;
111 	ret = regmap_write(llcc_bcast_regmap, drv->edac_reg_offset->drp_ecc_error_cfg,
113 	if (ret)
114 		return ret;
116 	ret = regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->cmn_interrupt_2_enable,
119 	if (ret)
120 		return ret;
122 	ret = regmap_write(llcc_bcast_regmap, drv->edac_reg_offset->drp_interrupt_enable,
124 	return ret;
131 	int ret;
136 		ret = regmap_write(drv->bcast_regmap,
139 		if (ret)
140 			return ret;
142 		ret = regmap_write(drv->bcast_regmap,
145 		if (ret)
146 			return ret;
150 		ret = regmap_write(drv->bcast_regmap,
153 		if (ret)
154 			return ret;
156 		ret = regmap_write(drv->bcast_regmap,
159 		if (ret)
160 			return ret;
163 		ret = -EINVAL;
167 	return ret;
211 	int err_cnt, err_ways, ret, i;
218 		ret = regmap_read(drv->regmaps[bank], synd_reg,
220 		if (ret)
227 	ret = regmap_read(drv->regmaps[bank], regs.count_status_reg,
229 	if (ret)
237 	ret = regmap_read(drv->regmaps[bank], regs.ways_status_reg,
239 	if (ret)
256 	int ret;
258 	ret = dump_syn_reg_values(drv, bank, err_type);
259 	if (ret)
260 		return ret;
280 		ret = -EINVAL;
285 	return ret;
294 	int ret;
298 		ret = regmap_read(drv->regmaps[i], drv->edac_reg_offset->drp_interrupt_status,
301 		if (!ret && (drp_error & SB_ECC_ERROR)) {
304 			ret = dump_syn_reg(edev_ctl, LLCC_DRAM_CE, i);
305 		} else if (!ret && (drp_error & DB_ECC_ERROR)) {
308 			ret = dump_syn_reg(edev_ctl, LLCC_DRAM_UE, i);
310 		if (!ret)
313 		ret = regmap_read(drv->regmaps[i], drv->edac_reg_offset->trp_interrupt_0_status,
316 		if (!ret && (trp_error & SB_ECC_ERROR)) {
319 			ret = dump_syn_reg(edev_ctl, LLCC_TRAM_CE, i);
320 		} else if (!ret && (trp_error & DB_ECC_ERROR)) {
323 			ret = dump_syn_reg(edev_ctl, LLCC_TRAM_UE, i);
325 		if (!ret)