drivers/edac/mce_amd.c

146 static bool f12h_mc0_mce(u16 ec, u8 xec)
150 	if (MEM_ERROR(ec)) {
151 		u8 ll = LL(ec);
157 			pr_cont("Data/Tag %s error.\n", R4_MSG(ec));
164 static bool f10h_mc0_mce(u16 ec, u8 xec)
166 	if (R4(ec) == R4_GEN && LL(ec) == LL_L1) {
170 	return f12h_mc0_mce(ec, xec);
173 static bool k8_mc0_mce(u16 ec, u8 xec)
175 	if (BUS_ERROR(ec)) {
180 	return f10h_mc0_mce(ec, xec);
183 static bool cat_mc0_mce(u16 ec, u8 xec)
185 	u8 r4	 = R4(ec);
188 	if (MEM_ERROR(ec)) {
190 		if (TT(ec) != TT_DATA || LL(ec) != LL_L1)
208 	} else if (BUS_ERROR(ec)) {
210 		if ((II(ec) != II_MEM && II(ec) != II_IO) || LL(ec) != LL_LG)
235 static bool f15h_mc0_mce(u16 ec, u8 xec)
239 	if (MEM_ERROR(ec)) {
270 	} else if (BUS_ERROR(ec)) {
276 	} else if (INT_ERROR(ec)) {
290 	u16 ec = EC(m->status);
296 	if (TLB_ERROR(ec)) {
297 		if (TT(ec) == TT_DATA) {
298 			pr_cont("%s TLB %s.\n", LL_MSG(ec),
303 	} else if (fam_ops.mc0_mce(ec, xec))
309 static bool k8_mc1_mce(u16 ec, u8 xec)
311 	u8 ll	 = LL(ec);
314 	if (!MEM_ERROR(ec))
320 		switch (R4(ec)) {
343 static bool cat_mc1_mce(u16 ec, u8 xec)
345 	u8 r4    = R4(ec);
348 	if (!MEM_ERROR(ec))
351 	if (TT(ec) != TT_INSTR)
368 static bool f15h_mc1_mce(u16 ec, u8 xec)
372 	if (!MEM_ERROR(ec))
400 	u16 ec = EC(m->status);
405 	if (TLB_ERROR(ec))
406 		pr_cont("%s TLB %s.\n", LL_MSG(ec),
408 	else if (BUS_ERROR(ec)) {
412 	} else if (INT_ERROR(ec)) {
417 	} else if (fam_ops.mc1_mce(ec, xec))
428 static bool k8_mc2_mce(u16 ec, u8 xec)
436 	else if (xec == 0x2 && MEM_ERROR(ec))
437 		pr_cont(": %s error in the L2 cache tags.\n", R4_MSG(ec));
439 		if (TLB_ERROR(ec))
441 				TT_MSG(ec));
442 		else if (BUS_ERROR(ec))
444 				R4_MSG(ec), PP_MSG(ec));
445 		else if (MEM_ERROR(ec)) {
446 			u8 r4 = R4(ec);
450 					R4_MSG(ec));
453 					"access from L2.\n", R4_MSG(ec));
464 static bool f15h_mc2_mce(u16 ec, u8 xec)
468 	if (TLB_ERROR(ec)) {
475 	} else if (BUS_ERROR(ec)) {
480 	} else if (MEM_ERROR(ec)) {
493 	} else if (INT_ERROR(ec)) {
503 static bool f16h_mc2_mce(u16 ec, u8 xec)
505 	u8 r4 = R4(ec);
507 	if (!MEM_ERROR(ec))
546 	u16 ec = EC(m->status);
551 	if (!fam_ops.mc2_mce(ec, xec))
557 	u16 ec = EC(m->status);
569 		u8 r4 = R4(ec);
571 		if (!BUS_ERROR(ec) || (r4 != R4_DRD && r4 != R4_DWR))
574 		pr_cont(" during %s.\n", R4_MSG(ec));
588 	u16 ec = EC(m->status);
612 		if (TLB_ERROR(ec))
614 		else if (BUS_ERROR(ec))
645 	u16 ec = EC(m->status);
653 	if (INT_ERROR(ec)) {
752 static inline void amd_decode_err_code(u16 ec)
754 	if (INT_ERROR(ec)) {
755 		pr_emerg(HW_ERR "internal: %s\n", UU_MSG(ec));
759 	pr_emerg(HW_ERR "cache level: %s", LL_MSG(ec));
761 	if (BUS_ERROR(ec))
762 		pr_cont(", mem/io: %s", II_MSG(ec));
764 		pr_cont(", tx: %s", TT_MSG(ec));
766 	if (MEM_ERROR(ec) || BUS_ERROR(ec)) {
767 		pr_cont(", mem-tx: %s", R4_MSG(ec));
769 		if (BUS_ERROR(ec))
770 			pr_cont(", part-proc: %s (%s)", PP_MSG(ec), TO_MSG(ec));