drivers/edac/armada_xp_edac.c

84 static uint32_t axp_mc_calc_address(struct axp_mc_drvdata *drvdata,
88 	if (drvdata->width == 8) {
90 		if (drvdata->cs_addr_sel[cs])
100 	} else if (drvdata->width == 4) {
102 		if (drvdata->cs_addr_sel[cs])
114 		if (drvdata->cs_addr_sel[cs])
129 	struct axp_mc_drvdata *drvdata = mci->pvt_info;
134 	char *msg = drvdata->msg;
136 	data_h    = readl(drvdata->base + SDRAM_ERR_DATA_H_REG);
137 	data_l    = readl(drvdata->base + SDRAM_ERR_DATA_L_REG);
138 	recv_ecc  = readl(drvdata->base + SDRAM_ERR_RECV_ECC_REG);
139 	calc_ecc  = readl(drvdata->base + SDRAM_ERR_CALC_ECC_REG);
140 	addr      = readl(drvdata->base + SDRAM_ERR_ADDR_REG);
141 	cnt_sbe   = readl(drvdata->base + SDRAM_ERR_SBE_COUNT_REG);
142 	cnt_dbe   = readl(drvdata->base + SDRAM_ERR_DBE_COUNT_REG);
143 	cause_err = readl(drvdata->base + SDRAM_ERR_CAUSE_ERR_REG);
144 	cause_msg = readl(drvdata->base + SDRAM_ERR_CAUSE_MSG_REG);
148 	       drvdata->base + SDRAM_ERR_CAUSE_ERR_REG);
150 	       drvdata->base + SDRAM_ERR_CAUSE_MSG_REG);
154 		writel(0, drvdata->base + SDRAM_ERR_SBE_COUNT_REG);
156 		writel(0, drvdata->base + SDRAM_ERR_DBE_COUNT_REG);
195 	addr_val = axp_mc_calc_address(drvdata, cs_val, bank_val, row_val,
209 				     mci->ctl_name, drvdata->msg);
217 				     mci->ctl_name, drvdata->msg);
223 	struct axp_mc_drvdata *drvdata = mci->pvt_info;
228 	config = readl(drvdata->base + SDRAM_CONFIG_REG);
231 		drvdata->width = 8;
234 		drvdata->width = 4;
236 	addr_ctrl = readl(drvdata->base + SDRAM_ADDR_CTRL_REG);
237 	rank_ctrl = readl(drvdata->base + SDRAM_RANK_CTRL_REG);
244 		drvdata->cs_addr_sel[i] =
287 	struct axp_mc_drvdata *drvdata;
310 	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*drvdata));
314 	drvdata = mci->pvt_info;
315 	drvdata->base = base;
333 		drvdata->width /= 2;
337 	writel(1 << SDRAM_ERR_CTRL_THR_OFFSET, drvdata->base + SDRAM_ERR_CTRL_REG);
340 	writel(~(SDRAM_ERR_CAUSE_DBE_MASK | SDRAM_ERR_CAUSE_SBE_MASK), drvdata->base + SDRAM_ERR_CAUSE_ERR_REG);
341 	writel(~(SDRAM_ERR_CAUSE_DBE_MASK | SDRAM_ERR_CAUSE_SBE_MASK), drvdata->base + SDRAM_ERR_CAUSE_MSG_REG);
344 	writel(0, drvdata->base + SDRAM_ERR_SBE_COUNT_REG);
345 	writel(0, drvdata->base + SDRAM_ERR_DBE_COUNT_REG);
390 static void aurora_l2_inject(struct aurora_l2_drvdata *drvdata)
392 	drvdata->inject_addr &= AURORA_ERR_INJECT_CTL_ADDR_MASK;
393 	drvdata->inject_ctl &= AURORA_ERR_INJECT_CTL_EN_MASK;
394 	writel(0, drvdata->base + AURORA_ERR_INJECT_CTL_REG);
395 	writel(drvdata->inject_mask, drvdata->base + AURORA_ERR_INJECT_MASK_REG);
396 	writel(drvdata->inject_addr | drvdata->inject_ctl, drvdata->base + AURORA_ERR_INJECT_CTL_REG);
402 	struct aurora_l2_drvdata *drvdata = dci->pvt_info;
405 	char *msg = drvdata->msg;
406 	size_t size = sizeof(drvdata->msg);
409 	cnt = readl(drvdata->base + AURORA_ERR_CNT_REG);
410 	attr_cap = readl(drvdata->base + AURORA_ERR_ATTR_CAP_REG);
411 	addr_cap = readl(drvdata->base + AURORA_ERR_ADDR_CAP_REG);
412 	way_cap = readl(drvdata->base + AURORA_ERR_WAY_CAP_REG);
418 		writel(AURORA_ERR_CNT_CLR, drvdata->base + AURORA_ERR_CNT_REG);
467 	writel(AURORA_ERR_ATTR_CAP_VALID, drvdata->base + AURORA_ERR_ATTR_CAP_REG);
472 		edac_device_handle_ue(dci, 0, 0, drvdata->msg);
476 		edac_device_handle_ce(dci, 0, 0, drvdata->msg);
490 	struct aurora_l2_drvdata *drvdata = dci->pvt_info;
495 	aurora_l2_inject(drvdata);
507 	struct aurora_l2_drvdata *drvdata;
525 	dci = edac_device_alloc_ctl_info(sizeof(*drvdata),
530 	drvdata = dci->pvt_info;
531 	drvdata->base = base;
542 	writel(AURORA_ERR_CNT_CLR, drvdata->base + AURORA_ERR_CNT_REG);
543 	writel(AURORA_ERR_ATTR_CAP_VALID, drvdata->base + AURORA_ERR_ATTR_CAP_REG);
551 	drvdata->debugfs = edac_debugfs_create_dir(dev_name(&pdev->dev));
552 	if (drvdata->debugfs) {
554 					drvdata->debugfs,
555 					&drvdata->inject_addr);
557 					drvdata->debugfs,
558 					&drvdata->inject_mask);
560 				       drvdata->debugfs, &drvdata->inject_ctl);
571 	struct aurora_l2_drvdata *drvdata = dci->pvt_info;
573 	edac_debugfs_remove_recursive(drvdata->debugfs);