drivers/edac/amd64_edac.c

290 	 * Here we discard bits 63-40.  See section 3.4.2 of AMD publication
314 	 * Here we use the DRAM Base (section 3.4.4.1) and DRAM Limit (section
476  * Obtain info from the DRAM Hole Address Register (section 3.4.8, pub #26094)
604 	return sprintf(buf, "0x%x\n", pvt->injection.section);
608  * store error injection section value which refers to one of 4 16-byte sections
627 		amd64_warn("%s: invalid section 0x%lx\n", __func__, value);
631 	pvt->injection.section = (u32) value;
645  * 16-byte (128-bit + ECC bits) section
718 	u32 section, word_bits;
725 	/* Form value to choose 16-byte section of cacheline */
726 	section = F10_NB_ARRAY_DRAM | SET_NB_ARRAY_ADDR(pvt->injection.section);
728 	amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section);
735 	edac_dbg(0, "section=0x%x word_bits=0x%x\n", section, word_bits);
750 	u32 section, word_bits, tmp;
758 	/* Form value to choose 16-byte section of cacheline */
759 	section = F10_NB_ARRAY_DRAM | SET_NB_ARRAY_ADDR(pvt->injection.section);
761 	amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section);
784 	edac_dbg(0, "section=0x%x word_bits=0x%x\n", section, word_bits);
831  * The first part of section 3.4.4 (p. 70) shows how the DRAM Base (section
832  * 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers are used to translate a
854  *    address from the SysAddr, as shown near the start of section 3.4.4 (p.70).
881 	 * section 3.4.4 (p. 70).  Although sys_addr is a 64-bit value, the k8
885 	 * section 3.4.2 of AMD publication 24592: AMD x86-64 Architecture
897  * (section 3.4.4.1).  Return the number of bits from a SysAddr that are used
920 	 * See the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E)
961  * Low (section 3.6.4.5) and MCA NB Address High (section 3.6.4.6) registers