Lines Matching refs:chan
141 #define ZYNQMP_DMA_DESC_SIZE(chan) (chan->desc_size)
143 #define to_chan(chan) container_of(chan, struct zynqmp_dma_chan, \
244 * @chan: Driver specific DMA channel
251 struct zynqmp_dma_chan *chan;
256 static inline void zynqmp_dma_writeq(struct zynqmp_dma_chan *chan, u32 reg,
259 lo_hi_writeq(value, chan->regs + reg);
264 * @chan: ZynqMP DMA DMA channel pointer
267 static void zynqmp_dma_update_desc_to_ctrlr(struct zynqmp_dma_chan *chan,
273 zynqmp_dma_writeq(chan, ZYNQMP_DMA_SRC_START_LSB, addr);
275 zynqmp_dma_writeq(chan, ZYNQMP_DMA_DST_START_LSB, addr);
280 * @chan: ZynqMP DMA channel pointer
283 static void zynqmp_dma_desc_config_eod(struct zynqmp_dma_chan *chan,
295 * @chan: ZynqMP DMA channel pointer
302 static void zynqmp_dma_config_sg_ll_desc(struct zynqmp_dma_chan *chan,
314 if (chan->is_dmacoherent) {
320 dma_addr_t addr = chan->desc_pool_p +
321 ((uintptr_t)sdesc - (uintptr_t)chan->desc_pool_v);
324 ddesc->nxtdscraddr = addr + ZYNQMP_DMA_DESC_SIZE(chan);
330 * @chan: ZynqMP DMA channel pointer
332 static void zynqmp_dma_init(struct zynqmp_dma_chan *chan)
336 writel(ZYNQMP_DMA_IDS_DEFAULT_MASK, chan->regs + ZYNQMP_DMA_IDS);
337 val = readl(chan->regs + ZYNQMP_DMA_ISR);
338 writel(val, chan->regs + ZYNQMP_DMA_ISR);
340 if (chan->is_dmacoherent) {
344 writel(val, chan->regs + ZYNQMP_DMA_DSCR_ATTR);
347 val = readl(chan->regs + ZYNQMP_DMA_DATA_ATTR);
348 if (chan->is_dmacoherent) {
354 writel(val, chan->regs + ZYNQMP_DMA_DATA_ATTR);
357 val = readl(chan->regs + ZYNQMP_DMA_IRQ_SRC_ACCT);
358 val = readl(chan->regs + ZYNQMP_DMA_IRQ_DST_ACCT);
360 chan->idle = true;
371 struct zynqmp_dma_chan *chan = to_chan(tx->chan);
377 spin_lock_irqsave(&chan->lock, irqflags);
380 if (!list_empty(&chan->pending_list)) {
381 desc = list_last_entry(&chan->pending_list,
392 list_add_tail(&new->node, &chan->pending_list);
393 spin_unlock_irqrestore(&chan->lock, irqflags);
400 * @chan: ZynqMP DMA channel pointer
405 zynqmp_dma_get_descriptor(struct zynqmp_dma_chan *chan)
410 spin_lock_irqsave(&chan->lock, irqflags);
411 desc = list_first_entry(&chan->free_list,
414 spin_unlock_irqrestore(&chan->lock, irqflags);
418 memset((void *)desc->src_v, 0, ZYNQMP_DMA_DESC_SIZE(chan));
419 memset((void *)desc->dst_v, 0, ZYNQMP_DMA_DESC_SIZE(chan));
426 * @chan: ZynqMP DMA channel pointer
429 static void zynqmp_dma_free_descriptor(struct zynqmp_dma_chan *chan,
434 chan->desc_free_cnt++;
435 list_move_tail(&sdesc->node, &chan->free_list);
437 chan->desc_free_cnt++;
438 list_move_tail(&child->node, &chan->free_list);
444 * @chan: ZynqMP DMA channel pointer
447 static void zynqmp_dma_free_desc_list(struct zynqmp_dma_chan *chan,
453 zynqmp_dma_free_descriptor(chan, desc);
464 struct zynqmp_dma_chan *chan = to_chan(dchan);
468 ret = pm_runtime_resume_and_get(chan->dev);
472 chan->sw_desc_pool = kcalloc(ZYNQMP_DMA_NUM_DESCS, sizeof(*desc),
474 if (!chan->sw_desc_pool)
477 chan->idle = true;
478 chan->desc_free_cnt = ZYNQMP_DMA_NUM_DESCS;
480 INIT_LIST_HEAD(&chan->free_list);
483 desc = chan->sw_desc_pool + i;
484 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
486 list_add_tail(&desc->node, &chan->free_list);
489 chan->desc_pool_v = dma_alloc_coherent(chan->dev,
490 (2 * ZYNQMP_DMA_DESC_SIZE(chan) *
492 &chan->desc_pool_p, GFP_KERNEL);
493 if (!chan->desc_pool_v)
497 desc = chan->sw_desc_pool + i;
498 desc->src_v = (struct zynqmp_dma_desc_ll *) (chan->desc_pool_v +
499 (i * ZYNQMP_DMA_DESC_SIZE(chan) * 2));
501 desc->src_p = chan->desc_pool_p +
502 (i * ZYNQMP_DMA_DESC_SIZE(chan) * 2);
503 desc->dst_p = desc->src_p + ZYNQMP_DMA_DESC_SIZE(chan);
511 * @chan: ZynqMP DMA channel pointer
513 static void zynqmp_dma_start(struct zynqmp_dma_chan *chan)
515 writel(ZYNQMP_DMA_INT_EN_DEFAULT_MASK, chan->regs + ZYNQMP_DMA_IER);
516 writel(0, chan->regs + ZYNQMP_DMA_TOTAL_BYTE);
517 chan->idle = false;
518 writel(ZYNQMP_DMA_ENABLE, chan->regs + ZYNQMP_DMA_CTRL2);
523 * @chan: ZynqMP DMA channel pointer
526 static void zynqmp_dma_handle_ovfl_int(struct zynqmp_dma_chan *chan, u32 status)
529 writel(0, chan->regs + ZYNQMP_DMA_TOTAL_BYTE);
531 readl(chan->regs + ZYNQMP_DMA_IRQ_DST_ACCT);
533 readl(chan->regs + ZYNQMP_DMA_IRQ_SRC_ACCT);
536 static void zynqmp_dma_config(struct zynqmp_dma_chan *chan)
540 val = readl(chan->regs + ZYNQMP_DMA_CTRL0);
542 writel(val, chan->regs + ZYNQMP_DMA_CTRL0);
544 val = readl(chan->regs + ZYNQMP_DMA_DATA_ATTR);
545 burst_val = __ilog2_u32(chan->src_burst_len);
548 burst_val = __ilog2_u32(chan->dst_burst_len);
551 writel(val, chan->regs + ZYNQMP_DMA_DATA_ATTR);
564 struct zynqmp_dma_chan *chan = to_chan(dchan);
566 chan->src_burst_len = clamp(config->src_maxburst, 1U,
568 chan->dst_burst_len = clamp(config->dst_maxburst, 1U,
576 * @chan: ZynqMP DMA channel pointer
578 static void zynqmp_dma_start_transfer(struct zynqmp_dma_chan *chan)
582 if (!chan->idle)
585 zynqmp_dma_config(chan);
587 desc = list_first_entry_or_null(&chan->pending_list,
592 list_splice_tail_init(&chan->pending_list, &chan->active_list);
593 zynqmp_dma_update_desc_to_ctrlr(chan, desc);
594 zynqmp_dma_start(chan);
600 * @chan: ZynqMP DMA channel
602 static void zynqmp_dma_chan_desc_cleanup(struct zynqmp_dma_chan *chan)
607 spin_lock_irqsave(&chan->lock, irqflags);
609 list_for_each_entry_safe(desc, next, &chan->done_list, node) {
614 spin_unlock_irqrestore(&chan->lock, irqflags);
616 spin_lock_irqsave(&chan->lock, irqflags);
620 zynqmp_dma_free_descriptor(chan, desc);
623 spin_unlock_irqrestore(&chan->lock, irqflags);
628 * @chan: ZynqMP DMA channel pointer
630 static void zynqmp_dma_complete_descriptor(struct zynqmp_dma_chan *chan)
634 desc = list_first_entry_or_null(&chan->active_list,
640 list_add_tail(&desc->node, &chan->done_list);
649 struct zynqmp_dma_chan *chan = to_chan(dchan);
652 spin_lock_irqsave(&chan->lock, irqflags);
653 zynqmp_dma_start_transfer(chan);
654 spin_unlock_irqrestore(&chan->lock, irqflags);
659 * @chan: ZynqMP DMA channel pointer
661 static void zynqmp_dma_free_descriptors(struct zynqmp_dma_chan *chan)
665 spin_lock_irqsave(&chan->lock, irqflags);
666 zynqmp_dma_free_desc_list(chan, &chan->active_list);
667 zynqmp_dma_free_desc_list(chan, &chan->pending_list);
668 zynqmp_dma_free_desc_list(chan, &chan->done_list);
669 spin_unlock_irqrestore(&chan->lock, irqflags);
678 struct zynqmp_dma_chan *chan = to_chan(dchan);
680 zynqmp_dma_free_descriptors(chan);
681 dma_free_coherent(chan->dev,
682 (2 * ZYNQMP_DMA_DESC_SIZE(chan) * ZYNQMP_DMA_NUM_DESCS),
683 chan->desc_pool_v, chan->desc_pool_p);
684 kfree(chan->sw_desc_pool);
685 pm_runtime_mark_last_busy(chan->dev);
686 pm_runtime_put_autosuspend(chan->dev);
691 * @chan: ZynqMP DMA channel pointer
693 static void zynqmp_dma_reset(struct zynqmp_dma_chan *chan)
697 writel(ZYNQMP_DMA_IDS_DEFAULT_MASK, chan->regs + ZYNQMP_DMA_IDS);
699 spin_lock_irqsave(&chan->lock, irqflags);
700 zynqmp_dma_complete_descriptor(chan);
701 spin_unlock_irqrestore(&chan->lock, irqflags);
702 zynqmp_dma_chan_desc_cleanup(chan);
703 zynqmp_dma_free_descriptors(chan);
705 zynqmp_dma_init(chan);
717 struct zynqmp_dma_chan *chan = (struct zynqmp_dma_chan *)data;
721 isr = readl(chan->regs + ZYNQMP_DMA_ISR);
722 imr = readl(chan->regs + ZYNQMP_DMA_IMR);
725 writel(isr, chan->regs + ZYNQMP_DMA_ISR);
727 tasklet_schedule(&chan->tasklet);
732 chan->idle = true;
735 chan->err = true;
736 tasklet_schedule(&chan->tasklet);
737 dev_err(chan->dev, "Channel %p has errors\n", chan);
742 zynqmp_dma_handle_ovfl_int(chan, status);
743 dev_dbg(chan->dev, "Channel %p overflow interrupt\n", chan);
756 struct zynqmp_dma_chan *chan = from_tasklet(chan, t, tasklet);
760 if (chan->err) {
761 zynqmp_dma_reset(chan);
762 chan->err = false;
766 spin_lock_irqsave(&chan->lock, irqflags);
767 count = readl(chan->regs + ZYNQMP_DMA_IRQ_DST_ACCT);
769 zynqmp_dma_complete_descriptor(chan);
772 spin_unlock_irqrestore(&chan->lock, irqflags);
774 zynqmp_dma_chan_desc_cleanup(chan);
776 if (chan->idle) {
777 spin_lock_irqsave(&chan->lock, irqflags);
778 zynqmp_dma_start_transfer(chan);
779 spin_unlock_irqrestore(&chan->lock, irqflags);
791 struct zynqmp_dma_chan *chan = to_chan(dchan);
793 writel(ZYNQMP_DMA_IDS_DEFAULT_MASK, chan->regs + ZYNQMP_DMA_IDS);
794 zynqmp_dma_free_descriptors(chan);
805 struct zynqmp_dma_chan *chan = to_chan(dchan);
807 tasklet_kill(&chan->tasklet);
824 struct zynqmp_dma_chan *chan;
831 chan = to_chan(dchan);
835 spin_lock_irqsave(&chan->lock, irqflags);
836 if (desc_cnt > chan->desc_free_cnt) {
837 spin_unlock_irqrestore(&chan->lock, irqflags);
838 dev_dbg(chan->dev, "chan %p descs are not available\n", chan);
841 chan->desc_free_cnt = chan->desc_free_cnt - desc_cnt;
842 spin_unlock_irqrestore(&chan->lock, irqflags);
846 new = zynqmp_dma_get_descriptor(chan);
850 zynqmp_dma_config_sg_ll_desc(chan, desc, dma_src,
862 zynqmp_dma_desc_config_eod(chan, desc);
870 * @chan: ZynqMP DMA channel pointer
872 static void zynqmp_dma_chan_remove(struct zynqmp_dma_chan *chan)
874 if (!chan)
877 if (chan->irq)
878 devm_free_irq(chan->zdev->dev, chan->irq, chan);
879 tasklet_kill(&chan->tasklet);
880 list_del(&chan->common.device_node);
893 struct zynqmp_dma_chan *chan;
897 chan = devm_kzalloc(zdev->dev, sizeof(*chan), GFP_KERNEL);
898 if (!chan)
900 chan->dev = zdev->dev;
901 chan->zdev = zdev;
903 chan->regs = devm_platform_ioremap_resource(pdev, 0);
904 if (IS_ERR(chan->regs))
905 return PTR_ERR(chan->regs);
907 chan->bus_width = ZYNQMP_DMA_BUS_WIDTH_64;
908 chan->dst_burst_len = ZYNQMP_DMA_MAX_DST_BURST_LEN;
909 chan->src_burst_len = ZYNQMP_DMA_MAX_SRC_BURST_LEN;
910 err = of_property_read_u32(node, "xlnx,bus-width", &chan->bus_width);
916 if (chan->bus_width != ZYNQMP_DMA_BUS_WIDTH_64 &&
917 chan->bus_width != ZYNQMP_DMA_BUS_WIDTH_128) {
922 chan->is_dmacoherent = of_property_read_bool(node, "dma-coherent");
923 zdev->chan = chan;
924 tasklet_setup(&chan->tasklet, zynqmp_dma_do_tasklet);
925 spin_lock_init(&chan->lock);
926 INIT_LIST_HEAD(&chan->active_list);
927 INIT_LIST_HEAD(&chan->pending_list);
928 INIT_LIST_HEAD(&chan->done_list);
929 INIT_LIST_HEAD(&chan->free_list);
931 dma_cookie_init(&chan->common);
932 chan->common.device = &zdev->common;
933 list_add_tail(&chan->common.device_node, &zdev->common.channels);
935 zynqmp_dma_init(chan);
936 chan->irq = platform_get_irq(pdev, 0);
937 if (chan->irq < 0)
939 err = devm_request_irq(&pdev->dev, chan->irq, zynqmp_dma_irq_handler, 0,
940 "zynqmp-dma", chan);
944 chan->desc_size = sizeof(struct zynqmp_dma_desc_ll);
945 chan->idle = true;
961 return dma_get_slave_channel(&zdev->chan->common);
1113 p->dst_addr_widths = BIT(zdev->chan->bus_width / 8);
1114 p->src_addr_widths = BIT(zdev->chan->bus_width / 8);
1136 zynqmp_dma_chan_remove(zdev->chan);
1157 zynqmp_dma_chan_remove(zdev->chan);