dma/xilinx/xilinx_dpdma.c

511 	struct xilinx_dpdma_hw_desc *hw_desc = &sw_desc->hw;
514 	hw_desc->src_addr = lower_32_bits(dma_addr[0]);
516 		hw_desc->addr_ext |=
521 		u32 *addr = &hw_desc->src_addr2;
526 			u32 *addr_ext = &hw_desc->addr_ext_23;
600 		struct xilinx_dpdma_hw_desc *hw_desc = &sw_desc->hw;
604 		dev_dbg(dev, "control: 0x%08x\n", hw_desc->control);
605 		dev_dbg(dev, "desc_id: 0x%08x\n", hw_desc->desc_id);
606 		dev_dbg(dev, "xfer_size: 0x%08x\n", hw_desc->xfer_size);
607 		dev_dbg(dev, "hsize_stride: 0x%08x\n", hw_desc->hsize_stride);
608 		dev_dbg(dev, "timestamp_lsb: 0x%08x\n", hw_desc->timestamp_lsb);
609 		dev_dbg(dev, "timestamp_msb: 0x%08x\n", hw_desc->timestamp_msb);
610 		dev_dbg(dev, "addr_ext: 0x%08x\n", hw_desc->addr_ext);
611 		dev_dbg(dev, "next_desc: 0x%08x\n", hw_desc->next_desc);
612 		dev_dbg(dev, "src_addr: 0x%08x\n", hw_desc->src_addr);
613 		dev_dbg(dev, "addr_ext_23: 0x%08x\n", hw_desc->addr_ext_23);
614 		dev_dbg(dev, "addr_ext_45: 0x%08x\n", hw_desc->addr_ext_45);
615 		dev_dbg(dev, "src_addr2: 0x%08x\n", hw_desc->src_addr2);
616 		dev_dbg(dev, "src_addr3: 0x%08x\n", hw_desc->src_addr3);
617 		dev_dbg(dev, "src_addr4: 0x%08x\n", hw_desc->src_addr4);
618 		dev_dbg(dev, "src_addr5: 0x%08x\n", hw_desc->src_addr5);
619 		dev_dbg(dev, "crc: 0x%08x\n", hw_desc->crc);
690 	struct xilinx_dpdma_hw_desc *hw_desc;
714 	hw_desc = &sw_desc->hw;
716 	hw_desc->xfer_size = hsize * xt->numf;
717 	hw_desc->hsize_stride =
721 	hw_desc->control |= XILINX_DPDMA_DESC_CONTROL_PREEMBLE;
722 	hw_desc->control |= XILINX_DPDMA_DESC_CONTROL_COMPLETE_INTR;
723 	hw_desc->control |= XILINX_DPDMA_DESC_CONTROL_IGNORE_DONE;
724 	hw_desc->control |= XILINX_DPDMA_DESC_CONTROL_LAST_OF_FRAME;