dma/xilinx/xilinx_dpdma.c

495  * @sw_desc: The software descriptor in which to set DMA addresses
502  * descriptor DMA address is set to the DMA address of @sw_desc. @prev may be
503  * identical to @sw_desc for cyclic transfers.
506 					       struct xilinx_dpdma_sw_desc *sw_desc,
511 	struct xilinx_dpdma_hw_desc *hw_desc = &sw_desc->hw;
538 	prev->hw.next_desc = lower_32_bits(sw_desc->dma_addr);
542 				   upper_32_bits(sw_desc->dma_addr));
556 	struct xilinx_dpdma_sw_desc *sw_desc;
559 	sw_desc = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &dma_addr);
560 	if (!sw_desc)
563 	sw_desc->dma_addr = dma_addr;
565 	return sw_desc;
571  * @sw_desc: software descriptor to free
577 			       struct xilinx_dpdma_sw_desc *sw_desc)
579 	dma_pool_free(chan->desc_pool, sw_desc, sw_desc->dma_addr);
592 	struct xilinx_dpdma_sw_desc *sw_desc;
599 	list_for_each_entry(sw_desc, &tx_desc->descriptors, node) {
600 		struct xilinx_dpdma_hw_desc *hw_desc = &sw_desc->hw;
603 		dev_dbg(dev, "descriptor DMA addr: %pad\n", &sw_desc->dma_addr);
657 	struct xilinx_dpdma_sw_desc *sw_desc, *next;
665 	list_for_each_entry_safe(sw_desc, next, &desc->descriptors, node) {
666 		list_del(&sw_desc->node);
667 		xilinx_dpdma_chan_free_sw_desc(desc->chan, sw_desc);
689 	struct xilinx_dpdma_sw_desc *sw_desc;
705 	sw_desc = xilinx_dpdma_chan_alloc_sw_desc(chan);
706 	if (!sw_desc) {
711 	xilinx_dpdma_sw_desc_set_dma_addrs(chan->xdev, sw_desc, sw_desc,
714 	hw_desc = &sw_desc->hw;
726 	list_add_tail(&sw_desc->node, &tx_desc->descriptors);
829 	struct xilinx_dpdma_sw_desc *sw_desc;
859 	list_for_each_entry(sw_desc, &desc->descriptors, node)
860 		sw_desc->hw.desc_id = desc->vdesc.tx.cookie
863 	sw_desc = list_first_entry(&desc->descriptors,
866 		    lower_32_bits(sw_desc->dma_addr));
870 				       upper_32_bits(sw_desc->dma_addr)));
1074 	struct xilinx_dpdma_sw_desc *sw_desc;
1088 	sw_desc = list_first_entry(&pending->descriptors,
1090 	if (sw_desc->hw.desc_id != desc_id) {
1093 			chan->id, sw_desc->hw.desc_id, desc_id);