Lines Matching refs:chan
453 void (*start_transfer)(struct xilinx_dma_chan *chan);
454 int (*stop_transfer)(struct xilinx_dma_chan *chan);
490 * @chan: Driver specific DMA channel
509 struct xilinx_dma_chan *chan[XILINX_MCDMA_MAX_CHANS_PER_DEVICE];
526 #define to_xilinx_chan(chan) \
527 container_of(chan, struct xilinx_dma_chan, common)
530 #define xilinx_dma_poll_timeout(chan, reg, val, cond, delay_us, timeout_us) \
531 readl_poll_timeout_atomic(chan->xdev->regs + chan->ctrl_offset + reg, \
535 static inline u32 dma_read(struct xilinx_dma_chan *chan, u32 reg)
537 return ioread32(chan->xdev->regs + reg);
540 static inline void dma_write(struct xilinx_dma_chan *chan, u32 reg, u32 value)
542 iowrite32(value, chan->xdev->regs + reg);
545 static inline void vdma_desc_write(struct xilinx_dma_chan *chan, u32 reg,
548 dma_write(chan, chan->desc_offset + reg, value);
551 static inline u32 dma_ctrl_read(struct xilinx_dma_chan *chan, u32 reg)
553 return dma_read(chan, chan->ctrl_offset + reg);
556 static inline void dma_ctrl_write(struct xilinx_dma_chan *chan, u32 reg,
559 dma_write(chan, chan->ctrl_offset + reg, value);
562 static inline void dma_ctrl_clr(struct xilinx_dma_chan *chan, u32 reg,
565 dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) & ~clr);
568 static inline void dma_ctrl_set(struct xilinx_dma_chan *chan, u32 reg,
571 dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) | set);
576 * @chan: Driver specific VDMA channel
585 static inline void vdma_desc_write_64(struct xilinx_dma_chan *chan, u32 reg,
589 writel(value_lsb, chan->xdev->regs + chan->desc_offset + reg);
592 writel(value_msb, chan->xdev->regs + chan->desc_offset + reg + 4);
595 static inline void dma_writeq(struct xilinx_dma_chan *chan, u32 reg, u64 value)
597 lo_hi_writeq(value, chan->xdev->regs + chan->ctrl_offset + reg);
600 static inline void xilinx_write(struct xilinx_dma_chan *chan, u32 reg,
603 if (chan->ext_addr)
604 dma_writeq(chan, reg, addr);
606 dma_ctrl_write(chan, reg, addr);
609 static inline void xilinx_axidma_buf(struct xilinx_dma_chan *chan,
614 if (chan->ext_addr) {
623 static inline void xilinx_aximcdma_buf(struct xilinx_dma_chan *chan,
627 if (chan->ext_addr) {
664 * @chan: Driver specific DMA channel
669 xilinx_vdma_alloc_tx_segment(struct xilinx_dma_chan *chan)
674 segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys);
685 * @chan: Driver specific DMA channel
690 xilinx_cdma_alloc_tx_segment(struct xilinx_dma_chan *chan)
695 segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys);
706 * @chan: Driver specific DMA channel
711 xilinx_axidma_alloc_tx_segment(struct xilinx_dma_chan *chan)
716 spin_lock_irqsave(&chan->lock, flags);
717 if (!list_empty(&chan->free_seg_list)) {
718 segment = list_first_entry(&chan->free_seg_list,
723 spin_unlock_irqrestore(&chan->lock, flags);
726 dev_dbg(chan->dev, "Could not find free tx segment\n");
733 * @chan: Driver specific DMA channel
738 xilinx_aximcdma_alloc_tx_segment(struct xilinx_dma_chan *chan)
743 spin_lock_irqsave(&chan->lock, flags);
744 if (!list_empty(&chan->free_seg_list)) {
745 segment = list_first_entry(&chan->free_seg_list,
750 spin_unlock_irqrestore(&chan->lock, flags);
779 * @chan: Driver specific DMA channel
782 static void xilinx_dma_free_tx_segment(struct xilinx_dma_chan *chan,
787 list_add_tail(&segment->node, &chan->free_seg_list);
792 * @chan: Driver specific DMA channel
795 static void xilinx_mcdma_free_tx_segment(struct xilinx_dma_chan *chan,
801 list_add_tail(&segment->node, &chan->free_seg_list);
806 * @chan: Driver specific DMA channel
809 static void xilinx_cdma_free_tx_segment(struct xilinx_dma_chan *chan,
812 dma_pool_free(chan->desc_pool, segment, segment->phys);
817 * @chan: Driver specific DMA channel
820 static void xilinx_vdma_free_tx_segment(struct xilinx_dma_chan *chan,
823 dma_pool_free(chan->desc_pool, segment, segment->phys);
828 * @chan: Driver specific DMA channel
833 xilinx_dma_alloc_tx_descriptor(struct xilinx_dma_chan *chan)
848 * @chan: Driver specific DMA channel
852 xilinx_dma_free_tx_descriptor(struct xilinx_dma_chan *chan,
863 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
866 xilinx_vdma_free_tx_segment(chan, segment);
868 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
872 xilinx_cdma_free_tx_segment(chan, cdma_segment);
874 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
878 xilinx_dma_free_tx_segment(chan, axidma_segment);
884 xilinx_mcdma_free_tx_segment(chan, aximcdma_segment);
895 * @chan: Driver specific DMA channel
898 static void xilinx_dma_free_desc_list(struct xilinx_dma_chan *chan,
905 xilinx_dma_free_tx_descriptor(chan, desc);
911 * @chan: Driver specific DMA channel
913 static void xilinx_dma_free_descriptors(struct xilinx_dma_chan *chan)
917 spin_lock_irqsave(&chan->lock, flags);
919 xilinx_dma_free_desc_list(chan, &chan->pending_list);
920 xilinx_dma_free_desc_list(chan, &chan->done_list);
921 xilinx_dma_free_desc_list(chan, &chan->active_list);
923 spin_unlock_irqrestore(&chan->lock, flags);
932 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
935 dev_dbg(chan->dev, "Free all channel resources.\n");
937 xilinx_dma_free_descriptors(chan);
939 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
940 spin_lock_irqsave(&chan->lock, flags);
941 INIT_LIST_HEAD(&chan->free_seg_list);
942 spin_unlock_irqrestore(&chan->lock, flags);
945 dma_free_coherent(chan->dev, sizeof(*chan->seg_v) *
946 XILINX_DMA_NUM_DESCS, chan->seg_v,
947 chan->seg_p);
950 dma_free_coherent(chan->dev, sizeof(*chan->cyclic_seg_v),
951 chan->cyclic_seg_v, chan->cyclic_seg_p);
954 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) {
955 spin_lock_irqsave(&chan->lock, flags);
956 INIT_LIST_HEAD(&chan->free_seg_list);
957 spin_unlock_irqrestore(&chan->lock, flags);
960 dma_free_coherent(chan->dev, sizeof(*chan->seg_mv) *
961 XILINX_DMA_NUM_DESCS, chan->seg_mv,
962 chan->seg_p);
965 if (chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA &&
966 chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIMCDMA) {
967 dma_pool_destroy(chan->desc_pool);
968 chan->desc_pool = NULL;
975 * @chan: Driver specific dma channel
980 static u32 xilinx_dma_get_residue(struct xilinx_dma_chan *chan,
993 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
999 chan->xdev->max_buffer_len;
1000 } else if (chan->xdev->dma_config->dmatype ==
1007 chan->xdev->max_buffer_len;
1016 chan->xdev->max_buffer_len;
1025 * @chan: Driver specific dma channel
1029 static void xilinx_dma_chan_handle_cyclic(struct xilinx_dma_chan *chan,
1037 spin_unlock_irqrestore(&chan->lock, *flags);
1039 spin_lock_irqsave(&chan->lock, *flags);
1045 * @chan: Driver specific DMA channel
1047 static void xilinx_dma_chan_desc_cleanup(struct xilinx_dma_chan *chan)
1052 spin_lock_irqsave(&chan->lock, flags);
1054 list_for_each_entry_safe(desc, next, &chan->done_list, node) {
1058 xilinx_dma_chan_handle_cyclic(chan, desc, &flags);
1066 if (chan->direction == DMA_DEV_TO_MEM)
1077 spin_unlock_irqrestore(&chan->lock, flags);
1079 spin_lock_irqsave(&chan->lock, flags);
1083 xilinx_dma_free_tx_descriptor(chan, desc);
1089 if (chan->terminating)
1093 spin_unlock_irqrestore(&chan->lock, flags);
1102 struct xilinx_dma_chan *chan = from_tasklet(chan, t, tasklet);
1104 xilinx_dma_chan_desc_cleanup(chan);
1115 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1119 if (chan->desc_pool)
1126 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
1128 chan->seg_v = dma_alloc_coherent(chan->dev,
1129 sizeof(*chan->seg_v) * XILINX_DMA_NUM_DESCS,
1130 &chan->seg_p, GFP_KERNEL);
1131 if (!chan->seg_v) {
1132 dev_err(chan->dev,
1134 chan->id);
1143 chan->cyclic_seg_v = dma_alloc_coherent(chan->dev,
1144 sizeof(*chan->cyclic_seg_v),
1145 &chan->cyclic_seg_p,
1147 if (!chan->cyclic_seg_v) {
1148 dev_err(chan->dev,
1150 dma_free_coherent(chan->dev, sizeof(*chan->seg_v) *
1151 XILINX_DMA_NUM_DESCS, chan->seg_v,
1152 chan->seg_p);
1155 chan->cyclic_seg_v->phys = chan->cyclic_seg_p;
1158 chan->seg_v[i].hw.next_desc =
1159 lower_32_bits(chan->seg_p + sizeof(*chan->seg_v) *
1161 chan->seg_v[i].hw.next_desc_msb =
1162 upper_32_bits(chan->seg_p + sizeof(*chan->seg_v) *
1164 chan->seg_v[i].phys = chan->seg_p +
1165 sizeof(*chan->seg_v) * i;
1166 list_add_tail(&chan->seg_v[i].node,
1167 &chan->free_seg_list);
1169 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) {
1171 chan->seg_mv = dma_alloc_coherent(chan->dev,
1172 sizeof(*chan->seg_mv) *
1174 &chan->seg_p, GFP_KERNEL);
1175 if (!chan->seg_mv) {
1176 dev_err(chan->dev,
1178 chan->id);
1182 chan->seg_mv[i].hw.next_desc =
1183 lower_32_bits(chan->seg_p + sizeof(*chan->seg_mv) *
1185 chan->seg_mv[i].hw.next_desc_msb =
1186 upper_32_bits(chan->seg_p + sizeof(*chan->seg_mv) *
1188 chan->seg_mv[i].phys = chan->seg_p +
1189 sizeof(*chan->seg_mv) * i;
1190 list_add_tail(&chan->seg_mv[i].node,
1191 &chan->free_seg_list);
1193 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
1194 chan->desc_pool = dma_pool_create("xilinx_cdma_desc_pool",
1195 chan->dev,
1200 chan->desc_pool = dma_pool_create("xilinx_vdma_desc_pool",
1201 chan->dev,
1207 if (!chan->desc_pool &&
1208 ((chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA) &&
1209 chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIMCDMA)) {
1210 dev_err(chan->dev,
1212 chan->id);
1218 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
1222 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
1226 if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg)
1227 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
1235 * @chan: Driver specific DMA channel
1241 static int xilinx_dma_calc_copysize(struct xilinx_dma_chan *chan,
1247 chan->xdev->max_buffer_len);
1250 chan->xdev->common.copy_align) {
1256 (1 << chan->xdev->common.copy_align));
1273 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1283 spin_lock_irqsave(&chan->lock, flags);
1284 if (!list_empty(&chan->active_list)) {
1285 desc = list_last_entry(&chan->active_list,
1291 if (chan->has_sg && chan->xdev->dma_config->dmatype != XDMA_TYPE_VDMA)
1292 residue = xilinx_dma_get_residue(chan, desc);
1294 spin_unlock_irqrestore(&chan->lock, flags);
1303 * @chan: Driver specific DMA channel
1307 static int xilinx_dma_stop_transfer(struct xilinx_dma_chan *chan)
1311 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP);
1314 return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
1321 * @chan: Driver specific DMA channel
1325 static int xilinx_cdma_stop_transfer(struct xilinx_dma_chan *chan)
1329 return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
1336 * @chan: Driver specific DMA channel
1338 static void xilinx_dma_start(struct xilinx_dma_chan *chan)
1343 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP);
1346 err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
1351 dev_err(chan->dev, "Cannot start channel %p: %x\n",
1352 chan, dma_ctrl_read(chan, XILINX_DMA_REG_DMASR));
1354 chan->err = true;
1360 * @chan: Driver specific channel struct pointer
1362 static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan)
1364 struct xilinx_vdma_config *config = &chan->config;
1371 if (chan->err)
1374 if (!chan->idle)
1377 if (list_empty(&chan->pending_list))
1380 desc = list_first_entry(&chan->pending_list,
1384 if (chan->has_vflip) {
1385 reg = dma_read(chan, XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP);
1388 dma_write(chan, XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP,
1392 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
1405 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
1407 j = chan->desc_submitcount;
1408 reg = dma_read(chan, XILINX_DMA_REG_PARK_PTR);
1409 if (chan->direction == DMA_MEM_TO_DEV) {
1416 dma_write(chan, XILINX_DMA_REG_PARK_PTR, reg);
1419 xilinx_dma_start(chan);
1421 if (chan->err)
1425 if (chan->desc_submitcount < chan->num_frms)
1426 i = chan->desc_submitcount;
1429 if (chan->ext_addr)
1430 vdma_desc_write_64(chan,
1435 vdma_desc_write(chan,
1446 vdma_desc_write(chan, XILINX_DMA_REG_HSIZE, last->hw.hsize);
1447 vdma_desc_write(chan, XILINX_DMA_REG_FRMDLY_STRIDE,
1449 vdma_desc_write(chan, XILINX_DMA_REG_VSIZE, last->hw.vsize);
1451 chan->desc_submitcount++;
1452 chan->desc_pendingcount--;
1453 list_move_tail(&desc->node, &chan->active_list);
1454 if (chan->desc_submitcount == chan->num_frms)
1455 chan->desc_submitcount = 0;
1457 chan->idle = false;
1462 * @chan: Driver specific channel struct pointer
1464 static void xilinx_cdma_start_transfer(struct xilinx_dma_chan *chan)
1468 u32 ctrl_reg = dma_read(chan, XILINX_DMA_REG_DMACR);
1470 if (chan->err)
1473 if (!chan->idle)
1476 if (list_empty(&chan->pending_list))
1479 head_desc = list_first_entry(&chan->pending_list,
1481 tail_desc = list_last_entry(&chan->pending_list,
1486 if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) {
1488 ctrl_reg |= chan->desc_pendingcount <<
1490 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, ctrl_reg);
1493 if (chan->has_sg) {
1494 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,
1497 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
1500 xilinx_write(chan, XILINX_DMA_REG_CURDESC,
1504 xilinx_write(chan, XILINX_DMA_REG_TAILDESC,
1517 xilinx_write(chan, XILINX_CDMA_REG_SRCADDR,
1519 xilinx_write(chan, XILINX_CDMA_REG_DSTADDR,
1523 dma_ctrl_write(chan, XILINX_DMA_REG_BTT,
1524 hw->control & chan->xdev->max_buffer_len);
1527 list_splice_tail_init(&chan->pending_list, &chan->active_list);
1528 chan->desc_pendingcount = 0;
1529 chan->idle = false;
1534 * @chan: Driver specific channel struct pointer
1536 static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan)
1542 if (chan->err)
1545 if (list_empty(&chan->pending_list))
1548 if (!chan->idle)
1551 head_desc = list_first_entry(&chan->pending_list,
1553 tail_desc = list_last_entry(&chan->pending_list,
1558 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
1560 if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) {
1562 reg |= chan->desc_pendingcount <<
1564 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
1567 if (chan->has_sg)
1568 xilinx_write(chan, XILINX_DMA_REG_CURDESC,
1571 reg |= chan->irq_delay << XILINX_DMA_CR_DELAY_SHIFT;
1572 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
1574 xilinx_dma_start(chan);
1576 if (chan->err)
1580 if (chan->has_sg) {
1581 if (chan->cyclic)
1582 xilinx_write(chan, XILINX_DMA_REG_TAILDESC,
1583 chan->cyclic_seg_v->phys);
1585 xilinx_write(chan, XILINX_DMA_REG_TAILDESC,
1596 xilinx_write(chan, XILINX_DMA_REG_SRCDSTADDR,
1600 dma_ctrl_write(chan, XILINX_DMA_REG_BTT,
1601 hw->control & chan->xdev->max_buffer_len);
1604 list_splice_tail_init(&chan->pending_list, &chan->active_list);
1605 chan->desc_pendingcount = 0;
1606 chan->idle = false;
1611 * @chan: Driver specific channel struct pointer
1613 static void xilinx_mcdma_start_transfer(struct xilinx_dma_chan *chan)
1624 if (chan->err)
1627 if (!chan->idle)
1630 if (list_empty(&chan->pending_list))
1633 head_desc = list_first_entry(&chan->pending_list,
1635 tail_desc = list_last_entry(&chan->pending_list,
1640 reg = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest));
1642 if (chan->desc_pendingcount <= XILINX_MCDMA_COALESCE_MAX) {
1644 reg |= chan->desc_pendingcount <<
1649 dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg);
1652 xilinx_write(chan, XILINX_MCDMA_CHAN_CDESC_OFFSET(chan->tdest),
1656 reg = dma_ctrl_read(chan, XILINX_MCDMA_CHEN_OFFSET);
1657 reg |= BIT(chan->tdest);
1658 dma_ctrl_write(chan, XILINX_MCDMA_CHEN_OFFSET, reg);
1661 reg = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest));
1663 dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg);
1665 xilinx_dma_start(chan);
1667 if (chan->err)
1671 xilinx_write(chan, XILINX_MCDMA_CHAN_TDESC_OFFSET(chan->tdest),
1674 list_splice_tail_init(&chan->pending_list, &chan->active_list);
1675 chan->desc_pendingcount = 0;
1676 chan->idle = false;
1685 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1688 spin_lock_irqsave(&chan->lock, flags);
1689 chan->start_transfer(chan);
1690 spin_unlock_irqrestore(&chan->lock, flags);
1708 * @chan : xilinx DMA channel
1712 static void xilinx_dma_complete_descriptor(struct xilinx_dma_chan *chan)
1717 if (list_empty(&chan->active_list))
1720 list_for_each_entry_safe(desc, next, &chan->active_list, node) {
1721 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
1726 if (!(seg->hw.status & XILINX_DMA_BD_COMP_MASK) && chan->has_sg)
1729 if (chan->has_sg && chan->xdev->dma_config->dmatype !=
1731 desc->residue = xilinx_dma_get_residue(chan, desc);
1734 desc->err = chan->err;
1739 list_add_tail(&desc->node, &chan->done_list);
1745 * @chan: Driver specific DMA channel
1749 static int xilinx_dma_reset(struct xilinx_dma_chan *chan)
1754 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RESET);
1757 err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMACR, tmp,
1762 dev_err(chan->dev, "reset timeout, cr %x, sr %x\n",
1763 dma_ctrl_read(chan, XILINX_DMA_REG_DMACR),
1764 dma_ctrl_read(chan, XILINX_DMA_REG_DMASR));
1768 chan->err = false;
1769 chan->idle = true;
1770 chan->desc_pendingcount = 0;
1771 chan->desc_submitcount = 0;
1778 * @chan: Driver specific DMA channel
1782 static int xilinx_dma_chan_reset(struct xilinx_dma_chan *chan)
1787 err = xilinx_dma_reset(chan);
1792 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
1807 struct xilinx_dma_chan *chan = data;
1810 if (chan->direction == DMA_DEV_TO_MEM)
1816 chan_sermask = dma_ctrl_read(chan, ser_offset);
1822 if (chan->direction == DMA_DEV_TO_MEM)
1823 chan_offset = chan->xdev->dma_config->max_channels / 2;
1826 chan = chan->xdev->chan[chan_offset];
1828 status = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_SR_OFFSET(chan->tdest));
1832 dma_ctrl_write(chan, XILINX_MCDMA_CHAN_SR_OFFSET(chan->tdest),
1836 dev_err(chan->dev, "Channel %p has errors %x cdr %x tdr %x\n",
1837 chan,
1838 dma_ctrl_read(chan, XILINX_MCDMA_CH_ERR_OFFSET),
1839 dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CDESC_OFFSET
1840 (chan->tdest)),
1841 dma_ctrl_read(chan, XILINX_MCDMA_CHAN_TDESC_OFFSET
1842 (chan->tdest)));
1843 chan->err = true;
1851 dev_dbg(chan->dev, "Inter-packet latency too long\n");
1855 spin_lock(&chan->lock);
1856 xilinx_dma_complete_descriptor(chan);
1857 chan->idle = true;
1858 chan->start_transfer(chan);
1859 spin_unlock(&chan->lock);
1862 tasklet_hi_schedule(&chan->tasklet);
1875 struct xilinx_dma_chan *chan = data;
1879 status = dma_ctrl_read(chan, XILINX_DMA_REG_DMASR);
1883 dma_ctrl_write(chan, XILINX_DMA_REG_DMASR,
1896 dma_ctrl_write(chan, XILINX_DMA_REG_DMASR,
1899 if (!chan->flush_on_fsync ||
1901 dev_err(chan->dev,
1903 chan, errors,
1904 dma_ctrl_read(chan, XILINX_DMA_REG_CURDESC),
1905 dma_ctrl_read(chan, XILINX_DMA_REG_TAILDESC));
1906 chan->err = true;
1912 spin_lock(&chan->lock);
1913 xilinx_dma_complete_descriptor(chan);
1914 chan->idle = true;
1915 chan->start_transfer(chan);
1916 spin_unlock(&chan->lock);
1919 tasklet_schedule(&chan->tasklet);
1925 * @chan: Driver specific dma channel
1928 static void append_desc_queue(struct xilinx_dma_chan *chan,
1937 if (list_empty(&chan->pending_list))
1944 tail_desc = list_last_entry(&chan->pending_list,
1946 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
1951 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
1956 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
1974 list_add_tail(&desc->node, &chan->pending_list);
1975 chan->desc_pendingcount++;
1977 if (chan->has_sg && (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA)
1978 && unlikely(chan->desc_pendingcount > chan->num_frms)) {
1979 dev_dbg(chan->dev, "desc pendingcount is too high\n");
1980 chan->desc_pendingcount = chan->num_frms;
1993 struct xilinx_dma_chan *chan = to_xilinx_chan(tx->chan);
1998 if (chan->cyclic) {
1999 xilinx_dma_free_tx_descriptor(chan, desc);
2003 if (chan->err) {
2008 err = xilinx_dma_chan_reset(chan);
2013 spin_lock_irqsave(&chan->lock, flags);
2018 append_desc_queue(chan, desc);
2021 chan->cyclic = true;
2023 chan->terminating = false;
2025 spin_unlock_irqrestore(&chan->lock, flags);
2044 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2063 desc = xilinx_dma_alloc_tx_descriptor(chan);
2067 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
2072 segment = xilinx_vdma_alloc_tx_segment(chan);
2082 hw->stride |= chan->config.frm_dly <<
2086 if (chan->ext_addr) {
2093 if (chan->ext_addr) {
2112 xilinx_dma_free_tx_descriptor(chan, desc);
2130 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2135 if (!len || len > chan->xdev->max_buffer_len)
2138 desc = xilinx_dma_alloc_tx_descriptor(chan);
2142 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
2146 segment = xilinx_cdma_alloc_tx_segment(chan);
2154 if (chan->ext_addr) {
2168 xilinx_dma_free_tx_descriptor(chan, desc);
2188 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2201 desc = xilinx_dma_alloc_tx_descriptor(chan);
2205 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
2217 segment = xilinx_axidma_alloc_tx_segment(chan);
2225 copy = xilinx_dma_calc_copysize(chan, sg_dma_len(sg),
2230 xilinx_axidma_buf(chan, hw, sg_dma_address(sg),
2235 if (chan->direction == DMA_MEM_TO_DEV) {
2256 if (chan->direction == DMA_MEM_TO_DEV) {
2264 if (chan->xdev->has_axistream_connected)
2270 xilinx_dma_free_tx_descriptor(chan, desc);
2290 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2310 desc = xilinx_dma_alloc_tx_descriptor(chan);
2314 chan->direction = direction;
2315 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
2325 segment = xilinx_axidma_alloc_tx_segment(chan);
2333 copy = xilinx_dma_calc_copysize(chan, period_len,
2336 xilinx_axidma_buf(chan, hw, buf_addr, sg_used,
2359 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
2361 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
2377 xilinx_dma_free_tx_descriptor(chan, desc);
2398 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2411 desc = xilinx_dma_alloc_tx_descriptor(chan);
2415 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
2427 segment = xilinx_aximcdma_alloc_tx_segment(chan);
2436 chan->xdev->max_buffer_len);
2440 xilinx_aximcdma_buf(chan, hw, sg_dma_address(sg),
2444 if (chan->direction == DMA_MEM_TO_DEV && app_w) {
2463 if (chan->direction == DMA_MEM_TO_DEV) {
2474 xilinx_dma_free_tx_descriptor(chan, desc);
2487 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2491 if (!chan->cyclic) {
2492 err = chan->stop_transfer(chan);
2494 dev_err(chan->dev, "Cannot stop channel %p: %x\n",
2495 chan, dma_ctrl_read(chan,
2497 chan->err = true;
2501 xilinx_dma_chan_reset(chan);
2503 chan->terminating = true;
2504 xilinx_dma_free_descriptors(chan);
2505 chan->idle = true;
2507 if (chan->cyclic) {
2508 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
2510 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
2511 chan->cyclic = false;
2514 if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg)
2515 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,
2523 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2525 tasklet_kill(&chan->tasklet);
2544 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2548 return xilinx_dma_chan_reset(chan);
2550 dmacr = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
2552 chan->config.frm_dly = cfg->frm_dly;
2553 chan->config.park = cfg->park;
2556 chan->config.gen_lock = cfg->gen_lock;
2557 chan->config.master = cfg->master;
2560 if (cfg->gen_lock && chan->genlock) {
2566 chan->config.frm_cnt_en = cfg->frm_cnt_en;
2567 chan->config.vflip_en = cfg->vflip_en;
2570 chan->config.park_frm = cfg->park_frm;
2572 chan->config.park_frm = -1;
2574 chan->config.coalesc = cfg->coalesc;
2575 chan->config.delay = cfg->delay;
2580 chan->config.coalesc = cfg->coalesc;
2586 chan->config.delay = cfg->delay;
2593 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, dmacr);
2605 * @chan: Driver specific DMA channel
2607 static void xilinx_dma_chan_remove(struct xilinx_dma_chan *chan)
2610 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,
2613 if (chan->irq > 0)
2614 free_irq(chan->irq, chan);
2616 tasklet_kill(&chan->tasklet);
2618 list_del(&chan->common.device_node);
2812 struct xilinx_dma_chan *chan;
2818 chan = devm_kzalloc(xdev->dev, sizeof(*chan), GFP_KERNEL);
2819 if (!chan)
2822 chan->dev = xdev->dev;
2823 chan->xdev = xdev;
2824 chan->desc_pendingcount = 0x0;
2825 chan->ext_addr = xdev->ext_addr;
2831 chan->idle = true;
2833 spin_lock_init(&chan->lock);
2834 INIT_LIST_HEAD(&chan->pending_list);
2835 INIT_LIST_HEAD(&chan->done_list);
2836 INIT_LIST_HEAD(&chan->active_list);
2837 INIT_LIST_HEAD(&chan->free_seg_list);
2842 of_property_read_u8(node, "xlnx,irq-delay", &chan->irq_delay);
2844 chan->genlock = of_property_read_bool(node, "xlnx,genlock-mode");
2863 chan->direction = DMA_MEM_TO_DEV;
2864 chan->id = xdev->mm2s_chan_id++;
2865 chan->tdest = chan->id;
2867 chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET;
2869 chan->desc_offset = XILINX_VDMA_MM2S_DESC_OFFSET;
2870 chan->config.park = 1;
2874 chan->flush_on_fsync = true;
2880 chan->direction = DMA_DEV_TO_MEM;
2881 chan->id = xdev->s2mm_chan_id++;
2882 chan->tdest = chan->id - xdev->dma_config->max_channels / 2;
2883 chan->has_vflip = of_property_read_bool(node,
2885 if (chan->has_vflip) {
2886 chan->config.vflip_en = dma_read(chan,
2892 chan->ctrl_offset = XILINX_MCDMA_S2MM_CTRL_OFFSET;
2894 chan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET;
2897 chan->desc_offset = XILINX_VDMA_S2MM_DESC_OFFSET;
2898 chan->config.park = 1;
2902 chan->flush_on_fsync = true;
2910 chan->irq = of_irq_get(node, chan->tdest);
2911 if (chan->irq < 0)
2912 return dev_err_probe(xdev->dev, chan->irq, "failed to get irq\n");
2913 err = request_irq(chan->irq, xdev->dma_config->irq_handler,
2914 IRQF_SHARED, "xilinx-dma-controller", chan);
2916 dev_err(xdev->dev, "unable to request IRQ %d\n", chan->irq);
2921 chan->start_transfer = xilinx_dma_start_transfer;
2922 chan->stop_transfer = xilinx_dma_stop_transfer;
2924 chan->start_transfer = xilinx_mcdma_start_transfer;
2925 chan->stop_transfer = xilinx_dma_stop_transfer;
2927 chan->start_transfer = xilinx_cdma_start_transfer;
2928 chan->stop_transfer = xilinx_cdma_stop_transfer;
2930 chan->start_transfer = xilinx_vdma_start_transfer;
2931 chan->stop_transfer = xilinx_dma_stop_transfer;
2937 dma_ctrl_read(chan, XILINX_DMA_REG_DMASR) &
2939 chan->has_sg = true;
2940 dev_dbg(chan->dev, "ch %d: SG %s\n", chan->id,
2941 chan->has_sg ? "enabled" : "disabled");
2945 tasklet_setup(&chan->tasklet, xilinx_dma_do_tasklet);
2951 chan->common.device = &xdev->common;
2953 list_add_tail(&chan->common.device_node, &xdev->common.channels);
2954 xdev->chan[chan->id] = chan;
2957 err = xilinx_dma_chan_reset(chan);
3008 if (chan_id >= xdev->dma_config->max_channels || !xdev->chan[chan_id])
3011 return dma_get_slave_channel(&xdev->chan[chan_id]->common);
3208 if (xdev->chan[i])
3209 xdev->chan[i]->num_frms = num_frames;
3240 if (xdev->chan[i])
3241 xilinx_dma_chan_remove(xdev->chan[i]);
3262 if (xdev->chan[i])
3263 xilinx_dma_chan_remove(xdev->chan[i]);