dma/xilinx/xdma.c

85  * @desc_num: Number of hardware descriptors
100 	u32				desc_num;
176 	last_blk_desc = (sw_desc->desc_num - 1) & XDMA_DESC_ADJACENT_MASK;
200 	for (i = 0; i < sw_desc->desc_num - 1; i++) {
264  * @desc_num: Number of hardware descriptors
268 xdma_alloc_desc(struct xdma_chan *chan, u32 desc_num, bool cyclic)
283 	sw_desc->desc_num = desc_num;
286 	dblk_num = DIV_ROUND_UP(desc_num, XDMA_DESC_ADJACENT);
367 		val = (desc->desc_num - 1) & XDMA_DESC_ADJACENT_MASK;
569 	u32 left = size, len, desc_num = filled_descs_num;
573 	dblk = sw_desc->desc_blocks + (desc_num / XDMA_DESC_ADJACENT);
575 	desc += desc_num & XDMA_DESC_ADJACENT_MASK;
582 		if (!(++desc_num & XDMA_DESC_ADJACENT_MASK))
592 	return desc_num - filled_descs_num;
612 	u32 desc_num = 0, i;
617 		desc_num += DIV_ROUND_UP(sg_dma_len(sg), XDMA_DESC_BLEN_MAX);
619 	sw_desc = xdma_alloc_desc(xdma_chan, desc_num, false);
636 	desc_num = 0;
639 		desc_num += xdma_fill_descs(sw_desc, *src, *dst, sg_dma_len(sg), desc_num);
676 	u32 desc_num;
713 	desc_num = 0;
715 		desc_num += xdma_fill_descs(sw_desc, *src, *dst, period_size, desc_num);
743 	u32 desc_num = 0, period_size = 0;
750 		desc_num += DIV_ROUND_UP(xt->sgl[i].size, XDMA_DESC_BLEN_MAX);
752 	sw_desc = xdma_alloc_desc(xchan, desc_num, false);
761 	desc_num = 0;
765 		desc_num += xdma_fill_descs(sw_desc, src_addr, dst_addr, xt->sgl[i].size, desc_num);
951 		if (desc->completed_desc_num == desc->desc_num) {
957 		if (desc->completed_desc_num > desc->desc_num ||