Lines Matching refs:od
253 struct omap_dmadev *od = to_omap_dma_dev(vd->tx.chan->device);
258 dma_pool_free(od->desc_pool, d->sg[i].t2_desc,
351 static void omap_dma_glbl_write(struct omap_dmadev *od, unsigned reg, unsigned val)
353 const struct omap_dma_reg *r = od->reg_map + reg;
357 omap_dma_write(val, r->type, od->base + r->offset);
360 static unsigned omap_dma_glbl_read(struct omap_dmadev *od, unsigned reg)
362 const struct omap_dma_reg *r = od->reg_map + reg;
366 return omap_dma_read(r->type, od->base + r->offset);
401 static void omap_dma_clear_lch(struct omap_dmadev *od, int lch)
406 c = od->lch_map[lch];
410 for (i = CSDP; i <= od->cfg->lch_end; i++)
414 static void omap_dma_assign(struct omap_dmadev *od, struct omap_chan *c,
417 c->channel_base = od->base + od->plat->channel_stride * lch;
419 od->lch_map[lch] = c;
424 struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
427 if (__dma_omap15xx(od->plat->dma_attr))
449 } else if (od->ll123_supported) {
487 struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
496 if (od->plat->errata & DMA_ERRATA_i541 && val & CCR_TRIGGER_SRC) {
499 sysconfig = omap_dma_glbl_read(od, OCP_SYSCONFIG);
502 omap_dma_glbl_write(od, OCP_SYSCONFIG, val);
511 omap_dma_glbl_write(od, OCP_SYSCONFIG, sysconfig);
525 if (!__dma_omap15xx(od->plat->dma_attr) && c->cyclic) {
633 struct omap_dmadev *od = devid;
636 spin_lock(&od->irq_lock);
638 status = omap_dma_glbl_read(od, IRQSTATUS_L1);
639 status &= od->irq_enable_mask;
641 spin_unlock(&od->irq_lock);
653 c = od->lch_map[channel];
656 dev_err(od->ddev.dev, "invalid channel %u\n", channel);
661 omap_dma_glbl_write(od, IRQSTATUS_L1, mask);
666 spin_unlock(&od->irq_lock);
671 static int omap_dma_get_lch(struct omap_dmadev *od, int *lch)
675 mutex_lock(&od->lch_lock);
676 channel = find_first_zero_bit(od->lch_bitmap, od->lch_count);
677 if (channel >= od->lch_count)
679 set_bit(channel, od->lch_bitmap);
680 mutex_unlock(&od->lch_lock);
682 omap_dma_clear_lch(od, channel);
688 mutex_unlock(&od->lch_lock);
694 static void omap_dma_put_lch(struct omap_dmadev *od, int lch)
696 omap_dma_clear_lch(od, lch);
697 mutex_lock(&od->lch_lock);
698 clear_bit(lch, od->lch_bitmap);
699 mutex_unlock(&od->lch_lock);
702 static inline bool omap_dma_legacy(struct omap_dmadev *od)
704 return IS_ENABLED(CONFIG_ARCH_OMAP1) && od->legacy;
709 struct omap_dmadev *od = to_omap_dma_dev(chan->device);
711 struct device *dev = od->ddev.dev;
714 if (omap_dma_legacy(od)) {
718 ret = omap_dma_get_lch(od, &c->dma_ch);
724 omap_dma_assign(od, c, c->dma_ch);
726 if (!omap_dma_legacy(od)) {
729 spin_lock_irq(&od->irq_lock);
731 omap_dma_glbl_write(od, IRQSTATUS_L1, val);
732 od->irq_enable_mask |= val;
733 omap_dma_glbl_write(od, IRQENABLE_L1, od->irq_enable_mask);
735 val = omap_dma_glbl_read(od, IRQENABLE_L0);
737 omap_dma_glbl_write(od, IRQENABLE_L0, val);
738 spin_unlock_irq(&od->irq_lock);
743 if (__dma_omap16xx(od->plat->dma_attr)) {
754 if (od->plat->errata & DMA_ERRATA_IFRAME_BUFFERING)
762 struct omap_dmadev *od = to_omap_dma_dev(chan->device);
765 if (!omap_dma_legacy(od)) {
766 spin_lock_irq(&od->irq_lock);
767 od->irq_enable_mask &= ~BIT(c->dma_ch);
768 omap_dma_glbl_write(od, IRQENABLE_L1, od->irq_enable_mask);
769 spin_unlock_irq(&od->irq_lock);
773 od->lch_map[c->dma_ch] = NULL;
776 if (omap_dma_legacy(od))
779 omap_dma_put_lch(od, c->dma_ch);
781 dev_dbg(od->ddev.dev, "freeing channel %u used for %u\n", c->dma_ch,
825 struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
829 if (val == 0 && od->plat->errata & DMA_ERRATA_3_3)
837 struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
840 if (__dma_omap15xx(od->plat->dma_attr)) {
863 struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
866 if (__dma_omap15xx(od->plat->dma_attr)) {
963 struct omap_dmadev *od = to_omap_dma_dev(chan->device);
1084 if (od->plat->errata & DMA_ERRATA_PARALLEL_CHANNELS)
1100 d->using_ll = od->ll123_supported;
1110 osg->t2_desc = dma_pool_alloc(od->desc_pool, GFP_ATOMIC,
1130 dma_pool_free(od->desc_pool, osg->t2_desc,
1144 struct omap_dmadev *od = to_omap_dma_dev(chan->device);
1231 if (__dma_omap15xx(od->plat->dma_attr))
1428 struct omap_dmadev *od = to_omap_dma_dev(chan->device);
1433 spin_lock_irqsave(&od->irq_lock, flags);
1473 spin_unlock_irqrestore(&od->irq_lock, flags);
1481 struct omap_dmadev *od = to_omap_dma_dev(chan->device);
1485 spin_lock_irqsave(&od->irq_lock, flags);
1497 spin_unlock_irqrestore(&od->irq_lock, flags);
1502 static int omap_dma_chan_init(struct omap_dmadev *od)
1510 c->reg_map = od->reg_map;
1512 vchan_init(&c->vc, &od->ddev);
1517 static void omap_dma_free(struct omap_dmadev *od)
1519 while (!list_empty(&od->ddev.channels)) {
1520 struct omap_chan *c = list_first_entry(&od->ddev.channels,
1530 static bool omap_dma_busy(struct omap_dmadev *od)
1536 lch = find_next_bit(od->lch_bitmap, od->lch_count, lch + 1);
1537 if (lch >= od->lch_count)
1539 c = od->lch_map[lch];
1553 struct omap_dmadev *od;
1555 od = container_of(nb, struct omap_dmadev, nb);
1559 if (omap_dma_busy(od))
1575 static void omap_dma_context_save(struct omap_dmadev *od)
1577 od->context.irqenable_l0 = omap_dma_glbl_read(od, IRQENABLE_L0);
1578 od->context.irqenable_l1 = omap_dma_glbl_read(od, IRQENABLE_L1);
1579 od->context.ocp_sysconfig = omap_dma_glbl_read(od, OCP_SYSCONFIG);
1580 od->context.gcr = omap_dma_glbl_read(od, GCR);
1583 static void omap_dma_context_restore(struct omap_dmadev *od)
1587 omap_dma_glbl_write(od, GCR, od->context.gcr);
1588 omap_dma_glbl_write(od, OCP_SYSCONFIG, od->context.ocp_sysconfig);
1589 omap_dma_glbl_write(od, IRQENABLE_L0, od->context.irqenable_l0);
1590 omap_dma_glbl_write(od, IRQENABLE_L1, od->context.irqenable_l1);
1593 if (od->plat->errata & DMA_ROMCODE_BUG)
1594 omap_dma_glbl_write(od, IRQSTATUS_L0, 0);
1597 for (i = 0; i < od->lch_count; i++)
1598 omap_dma_clear_lch(od, i);
1605 struct omap_dmadev *od;
1607 od = container_of(nb, struct omap_dmadev, nb);
1611 if (omap_dma_busy(od))
1613 omap_dma_context_save(od);
1618 omap_dma_context_restore(od);
1625 static void omap_dma_init_gcr(struct omap_dmadev *od, int arb_rate,
1631 if (!od->cfg->rw_priority)
1643 omap_dma_glbl_write(od, GCR, val);
1659 struct omap_dmadev *od;
1663 od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL);
1664 if (!od)
1667 od->base = devm_platform_ioremap_resource(pdev, 0);
1668 if (IS_ERR(od->base))
1669 return PTR_ERR(od->base);
1673 od->cfg = conf;
1674 od->plat = dev_get_platdata(&pdev->dev);
1675 if (!od->plat) {
1680 od->cfg = &default_cfg;
1682 od->plat = omap_get_plat_info();
1683 if (!od->plat)
1689 od->reg_map = od->plat->reg_map;
1691 dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
1692 dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask);
1693 dma_cap_set(DMA_MEMCPY, od->ddev.cap_mask);
1694 dma_cap_set(DMA_INTERLEAVE, od->ddev.cap_mask);
1695 od->ddev.device_alloc_chan_resources = omap_dma_alloc_chan_resources;
1696 od->ddev.device_free_chan_resources = omap_dma_free_chan_resources;
1697 od->ddev.device_tx_status = omap_dma_tx_status;
1698 od->ddev.device_issue_pending = omap_dma_issue_pending;
1699 od->ddev.device_prep_slave_sg = omap_dma_prep_slave_sg;
1700 od->ddev.device_prep_dma_cyclic = omap_dma_prep_dma_cyclic;
1701 od->ddev.device_prep_dma_memcpy = omap_dma_prep_dma_memcpy;
1702 od->ddev.device_prep_interleaved_dma = omap_dma_prep_dma_interleaved;
1703 od->ddev.device_config = omap_dma_slave_config;
1704 od->ddev.device_pause = omap_dma_pause;
1705 od->ddev.device_resume = omap_dma_resume;
1706 od->ddev.device_terminate_all = omap_dma_terminate_all;
1707 od->ddev.device_synchronize = omap_dma_synchronize;
1708 od->ddev.src_addr_widths = OMAP_DMA_BUSWIDTHS;
1709 od->ddev.dst_addr_widths = OMAP_DMA_BUSWIDTHS;
1710 od->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1711 if (__dma_omap15xx(od->plat->dma_attr))
1712 od->ddev.residue_granularity =
1715 od->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1716 od->ddev.max_burst = SZ_16M - 1; /* CCEN: 24bit unsigned */
1717 od->ddev.dev = &pdev->dev;
1718 INIT_LIST_HEAD(&od->ddev.channels);
1719 mutex_init(&od->lch_lock);
1720 spin_lock_init(&od->lock);
1721 spin_lock_init(&od->irq_lock);
1724 od->dma_requests = OMAP_SDMA_REQUESTS;
1727 &od->dma_requests)) {
1735 od->lch_count = od->plat->dma_attr->lch_count;
1736 if (unlikely(!od->lch_count))
1737 od->lch_count = OMAP_SDMA_CHANNELS;
1739 &od->lch_count)) {
1743 od->lch_count = OMAP_SDMA_CHANNELS;
1752 bitmap_from_arr32(od->lch_bitmap, &val, od->lch_count);
1754 if (od->plat->dma_attr->dev_caps & HS_CHANNELS_RESERVED)
1755 bitmap_set(od->lch_bitmap, 0, 2);
1757 od->lch_map = devm_kcalloc(&pdev->dev, od->lch_count,
1758 sizeof(*od->lch_map),
1760 if (!od->lch_map)
1763 for (i = 0; i < od->dma_requests; i++) {
1764 rc = omap_dma_chan_init(od);
1766 omap_dma_free(od);
1774 od->legacy = true;
1777 od->irq_enable_mask = 0;
1778 omap_dma_glbl_write(od, IRQENABLE_L1, 0);
1781 IRQF_SHARED, "omap-dma-engine", od);
1783 omap_dma_free(od);
1788 if (omap_dma_glbl_read(od, CAPS_0) & CAPS_0_SUPPORT_LL123)
1789 od->ll123_supported = true;
1791 od->ddev.filter.map = od->plat->slave_map;
1792 od->ddev.filter.mapcnt = od->plat->slavecnt;
1793 od->ddev.filter.fn = omap_dma_filter_fn;
1795 if (od->ll123_supported) {
1796 od->desc_pool = dma_pool_create(dev_name(&pdev->dev),
1800 if (!od->desc_pool) {
1803 od->ll123_supported = false;
1807 rc = dma_async_device_register(&od->ddev);
1811 omap_dma_free(od);
1815 platform_set_drvdata(pdev, od);
1818 omap_dma_info.dma_cap = od->ddev.cap_mask;
1825 dma_async_device_unregister(&od->ddev);
1826 omap_dma_free(od);
1830 omap_dma_init_gcr(od, DMA_DEFAULT_ARB_RATE, DMA_DEFAULT_FIFO_DEPTH, 0);
1832 if (od->cfg->needs_busy_check) {
1833 od->nb.notifier_call = omap_dma_busy_notifier;
1834 cpu_pm_register_notifier(&od->nb);
1835 } else if (od->cfg->may_lose_context) {
1836 od->nb.notifier_call = omap_dma_context_notifier;
1837 cpu_pm_register_notifier(&od->nb);
1841 od->ll123_supported ? " (LinkedList1/2/3 supported)" : "");
1848 struct omap_dmadev *od = platform_get_drvdata(pdev);
1851 if (od->cfg->may_lose_context)
1852 cpu_pm_unregister_notifier(&od->nb);
1858 devm_free_irq(&pdev->dev, irq, od);
1860 dma_async_device_unregister(&od->ddev);
1862 if (!omap_dma_legacy(od)) {
1864 omap_dma_glbl_write(od, IRQENABLE_L0, 0);
1867 if (od->ll123_supported)
1868 dma_pool_destroy(od->desc_pool);
1870 omap_dma_free(od);
1928 struct omap_dmadev *od = to_omap_dma_dev(chan->device);
1932 if (req <= od->dma_requests) {