Lines Matching defs:cdd
88 struct cppi41_dd *cdd;
254 static struct cppi41_channel *desc_to_chan(struct cppi41_dd *cdd, u32 desc)
262 if (!((desc >= cdd->descs_phys) &&
263 (desc < (cdd->descs_phys + descs_size)))) {
267 desc_num = (desc - cdd->descs_phys) / sizeof(struct cppi41_desc);
269 c = cdd->chan_busy[desc_num];
270 cdd->chan_busy[desc_num] = NULL;
273 pm_runtime_put(cdd->ddev.dev);
293 static u32 cppi41_pop_desc(struct cppi41_dd *cdd, unsigned queue_num)
297 desc = cppi_readl(cdd->qmgr_mem + QMGR_QUEUE_D(queue_num));
304 struct cppi41_dd *cdd = data;
305 u16 first_completion_queue = cdd->first_completion_queue;
306 u16 qmgr_num_pend = cdd->qmgr_num_pend;
315 val = cppi_readl(cdd->qmgr_mem + QMGR_PEND(i));
336 WARN_ON(cdd->is_suspended);
341 desc = cppi41_pop_desc(cdd, q_num);
342 c = desc_to_chan(cdd, desc);
374 struct cppi41_dd *cdd = c->cdd;
377 error = pm_runtime_get_sync(cdd->ddev.dev);
379 dev_err(cdd->ddev.dev, "%s pm runtime get: %i\n",
381 pm_runtime_put_noidle(cdd->ddev.dev);
393 pm_runtime_mark_last_busy(cdd->ddev.dev);
394 pm_runtime_put_autosuspend(cdd->ddev.dev);
402 struct cppi41_dd *cdd = c->cdd;
405 error = pm_runtime_get_sync(cdd->ddev.dev);
407 pm_runtime_put_noidle(cdd->ddev.dev);
412 WARN_ON(!list_empty(&cdd->pending));
414 pm_runtime_mark_last_busy(cdd->ddev.dev);
415 pm_runtime_put_autosuspend(cdd->ddev.dev);
433 struct cppi41_dd *cdd = c->cdd;
463 pm_runtime_get(cdd->ddev.dev);
466 desc_num = (desc_phys - cdd->descs_phys) / sizeof(struct cppi41_desc);
467 WARN_ON(cdd->chan_busy[desc_num]);
468 cdd->chan_busy[desc_num] = c;
472 cppi_writel(reg, cdd->qmgr_mem + QMGR_QUEUE_D(c->q_num));
476 * Caller must hold cdd->lock to prevent push_desc_queue()
480 static void cppi41_run_queue(struct cppi41_dd *cdd)
484 list_for_each_entry_safe(c, _c, &cdd->pending, node) {
493 struct cppi41_dd *cdd = c->cdd;
497 error = pm_runtime_get(cdd->ddev.dev);
499 pm_runtime_put_noidle(cdd->ddev.dev);
500 dev_err(cdd->ddev.dev, "Failed to pm_runtime_get: %i\n",
506 spin_lock_irqsave(&cdd->lock, flags);
507 list_add_tail(&c->node, &cdd->pending);
508 if (!cdd->is_suspended)
509 cppi41_run_queue(cdd);
510 spin_unlock_irqrestore(&cdd->lock, flags);
512 pm_runtime_mark_last_busy(cdd->ddev.dev);
513 pm_runtime_put_autosuspend(cdd->ddev.dev);
590 struct cppi41_dd *cdd = c->cdd;
596 error = pm_runtime_get(cdd->ddev.dev);
598 pm_runtime_put_noidle(cdd->ddev.dev);
603 if (cdd->is_suspended)
630 pm_runtime_mark_last_busy(cdd->ddev.dev);
631 pm_runtime_put_autosuspend(cdd->ddev.dev);
644 struct cppi41_dd *cdd = c->cdd;
650 td = cdd->cd;
651 td += cdd->first_td_desc;
653 td_desc_phys = cdd->descs_phys;
654 td_desc_phys += cdd->first_td_desc * sizeof(struct cppi41_desc);
662 cppi_writel(reg, cdd->qmgr_mem +
663 QMGR_QUEUE_D(cdd->td_queue.submit));
669 reg |= cdd->td_queue.complete;
679 desc_phys = cppi41_pop_desc(cdd, cdd->td_queue.complete);
681 desc_phys = cppi41_pop_desc(cdd, c->q_comp_num);
717 desc_phys = cppi41_pop_desc(cdd, c->q_num);
719 desc_phys = cppi41_pop_desc(cdd, c->q_comp_num);
739 struct cppi41_dd *cdd = c->cdd;
745 desc_num = (desc_phys - cdd->descs_phys) / sizeof(struct cppi41_desc);
746 if (!cdd->chan_busy[desc_num]) {
754 list_for_each_entry_safe(cc, _ct, &cdd->pending, node) {
767 WARN_ON(!cdd->chan_busy[desc_num]);
768 cdd->chan_busy[desc_num] = NULL;
771 pm_runtime_put(cdd->ddev.dev);
776 static int cppi41_add_chans(struct device *dev, struct cppi41_dd *cdd)
780 u32 n_chans = cdd->n_chans;
795 cchan->cdd = cdd;
797 cchan->gcr_reg = cdd->ctrl_mem + DMA_TXGCR(i >> 1);
800 cchan->gcr_reg = cdd->ctrl_mem + DMA_RXGCR(i >> 1);
804 cchan->desc = &cdd->cd[i];
805 cchan->desc_phys = cdd->descs_phys;
807 cchan->chan.device = &cdd->ddev;
808 list_add_tail(&cchan->chan.device_node, &cdd->ddev.channels);
810 cdd->first_td_desc = n_chans;
815 static void purge_descs(struct device *dev, struct cppi41_dd *cdd)
824 cppi_writel(0, cdd->qmgr_mem + QMGR_MEMBASE(i));
825 cppi_writel(0, cdd->qmgr_mem + QMGR_MEMCTRL(i));
827 dma_free_coherent(dev, mem_decs, cdd->cd,
828 cdd->descs_phys);
832 static void disable_sched(struct cppi41_dd *cdd)
834 cppi_writel(0, cdd->sched_mem + DMA_SCHED_CTRL);
837 static void deinit_cppi41(struct device *dev, struct cppi41_dd *cdd)
839 disable_sched(cdd);
841 purge_descs(dev, cdd);
843 cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM0_BASE);
844 cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM0_BASE);
845 dma_free_coherent(dev, QMGR_SCRATCH_SIZE, cdd->qmgr_scratch,
846 cdd->scratch_phys);
849 static int init_descs(struct device *dev, struct cppi41_dd *cdd)
873 cdd->cd = dma_alloc_coherent(dev, mem_decs,
874 &cdd->descs_phys, GFP_KERNEL);
875 if (!cdd->cd)
878 cppi_writel(cdd->descs_phys, cdd->qmgr_mem + QMGR_MEMBASE(i));
879 cppi_writel(reg, cdd->qmgr_mem + QMGR_MEMCTRL(i));
886 static void init_sched(struct cppi41_dd *cdd)
893 cppi_writel(0, cdd->sched_mem + DMA_SCHED_CTRL);
894 for (ch = 0; ch < cdd->n_chans; ch += 2) {
901 cppi_writel(reg, cdd->sched_mem + DMA_SCHED_WORD(word));
904 reg = cdd->n_chans * 2 - 1;
906 cppi_writel(reg, cdd->sched_mem + DMA_SCHED_CTRL);
909 static int init_cppi41(struct device *dev, struct cppi41_dd *cdd)
914 cdd->qmgr_scratch = dma_alloc_coherent(dev, QMGR_SCRATCH_SIZE,
915 &cdd->scratch_phys, GFP_KERNEL);
916 if (!cdd->qmgr_scratch)
919 cppi_writel(cdd->scratch_phys, cdd->qmgr_mem + QMGR_LRAM0_BASE);
920 cppi_writel(TOTAL_DESCS_NUM, cdd->qmgr_mem + QMGR_LRAM_SIZE);
921 cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM1_BASE);
923 ret = init_descs(dev, cdd);
927 cppi_writel(cdd->td_queue.submit, cdd->ctrl_mem + DMA_TDFDQ);
928 init_sched(cdd);
932 deinit_cppi41(dev, cdd);
949 struct cppi41_dd *cdd;
963 cdd = cchan->cdd;
965 queues = cdd->queues_tx;
967 queues = cdd->queues_rx;
1039 struct cppi41_dd *cdd;
1050 cdd = devm_kzalloc(&pdev->dev, sizeof(*cdd), GFP_KERNEL);
1051 if (!cdd)
1054 dma_cap_set(DMA_SLAVE, cdd->ddev.cap_mask);
1055 cdd->ddev.device_alloc_chan_resources = cppi41_dma_alloc_chan_resources;
1056 cdd->ddev.device_free_chan_resources = cppi41_dma_free_chan_resources;
1057 cdd->ddev.device_tx_status = cppi41_dma_tx_status;
1058 cdd->ddev.device_issue_pending = cppi41_dma_issue_pending;
1059 cdd->ddev.device_prep_slave_sg = cppi41_dma_prep_slave_sg;
1060 cdd->ddev.device_terminate_all = cppi41_stop_chan;
1061 cdd->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1062 cdd->ddev.src_addr_widths = CPPI41_DMA_BUSWIDTHS;
1063 cdd->ddev.dst_addr_widths = CPPI41_DMA_BUSWIDTHS;
1064 cdd->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1065 cdd->ddev.dev = dev;
1066 INIT_LIST_HEAD(&cdd->ddev.channels);
1067 cpp41_dma_info.dma_cap = cdd->ddev.cap_mask;
1074 cdd->ctrl_mem = devm_platform_ioremap_resource(pdev, index);
1075 if (IS_ERR(cdd->ctrl_mem))
1076 return PTR_ERR(cdd->ctrl_mem);
1078 cdd->sched_mem = devm_platform_ioremap_resource(pdev, index + 1);
1079 if (IS_ERR(cdd->sched_mem))
1080 return PTR_ERR(cdd->sched_mem);
1082 cdd->qmgr_mem = devm_platform_ioremap_resource(pdev, index + 2);
1083 if (IS_ERR(cdd->qmgr_mem))
1084 return PTR_ERR(cdd->qmgr_mem);
1086 spin_lock_init(&cdd->lock);
1087 INIT_LIST_HEAD(&cdd->pending);
1089 platform_set_drvdata(pdev, cdd);
1098 cdd->queues_rx = glue_info->queues_rx;
1099 cdd->queues_tx = glue_info->queues_tx;
1100 cdd->td_queue = glue_info->td_queue;
1101 cdd->qmgr_num_pend = glue_info->qmgr_num_pend;
1102 cdd->first_completion_queue = glue_info->first_completion_queue;
1106 "dma-channels", &cdd->n_chans);
1109 "#dma-channels", &cdd->n_chans);
1113 ret = init_cppi41(dev, cdd);
1117 ret = cppi41_add_chans(dev, cdd);
1128 dev_name(dev), cdd);
1131 cdd->irq = irq;
1133 ret = dma_async_device_register(&cdd->ddev);
1147 dma_async_device_unregister(&cdd->ddev);
1149 deinit_cppi41(dev, cdd);
1161 struct cppi41_dd *cdd = platform_get_drvdata(pdev);
1169 dma_async_device_unregister(&cdd->ddev);
1171 devm_free_irq(&pdev->dev, cdd->irq, cdd);
1172 deinit_cppi41(&pdev->dev, cdd);
1180 struct cppi41_dd *cdd = dev_get_drvdata(dev);
1182 cdd->dma_tdfdq = cppi_readl(cdd->ctrl_mem + DMA_TDFDQ);
1183 disable_sched(cdd);
1190 struct cppi41_dd *cdd = dev_get_drvdata(dev);
1195 cppi_writel(cdd->descs_phys, cdd->qmgr_mem + QMGR_MEMBASE(i));
1197 list_for_each_entry(c, &cdd->ddev.channels, chan.device_node)
1201 init_sched(cdd);
1203 cppi_writel(cdd->dma_tdfdq, cdd->ctrl_mem + DMA_TDFDQ);
1204 cppi_writel(cdd->scratch_phys, cdd->qmgr_mem + QMGR_LRAM0_BASE);
1205 cppi_writel(QMGR_SCRATCH_SIZE, cdd->qmgr_mem + QMGR_LRAM_SIZE);
1206 cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM1_BASE);
1213 struct cppi41_dd *cdd = dev_get_drvdata(dev);
1216 spin_lock_irqsave(&cdd->lock, flags);
1217 cdd->is_suspended = true;
1218 WARN_ON(!list_empty(&cdd->pending));
1219 spin_unlock_irqrestore(&cdd->lock, flags);
1226 struct cppi41_dd *cdd = dev_get_drvdata(dev);
1229 spin_lock_irqsave(&cdd->lock, flags);
1230 cdd->is_suspended = false;
1231 cppi41_run_queue(cdd);
1232 spin_unlock_irqrestore(&cdd->lock, flags);