Lines Matching defs:val
261 u32 reg, u32 val)
263 writel_relaxed(val, tdc->tdma->base_addr + tdc->chan_base_offset + reg);
377 u32 val;
379 val = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE);
380 val |= TEGRA_GPCDMA_CHAN_CSRE_PAUSE;
381 tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, val);
386 val,
387 !(val & TEGRA_GPCDMA_STATUS_BUSY),
417 u32 val;
419 val = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE);
420 val &= ~TEGRA_GPCDMA_CHAN_CSRE_PAUSE;
421 tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, val);
476 u32 val;
487 val,
488 (val & TEGRA_GPCDMA_STATUS_BUSY), 0,