drivers/dma/stm32-mdma.c

289 static u32 stm32_mdma_read(struct stm32_mdma_device *dmadev, u32 reg)
291 	return readl_relaxed(dmadev->base + reg);
294 static void stm32_mdma_write(struct stm32_mdma_device *dmadev, u32 reg, u32 val)
296 	writel_relaxed(val, dmadev->base + reg);
299 static void stm32_mdma_set_bits(struct stm32_mdma_device *dmadev, u32 reg,
302 	void __iomem *addr = dmadev->base + reg;
307 static void stm32_mdma_clr_bits(struct stm32_mdma_device *dmadev, u32 reg,
310 	void __iomem *addr = dmadev->base + reg;
406 	struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
414 	stm32_mdma_clr_bits(dmadev, reg, STM32_MDMA_CCR_IRQ_MASK);
416 	ccr = stm32_mdma_read(dmadev, reg);
418 		stm32_mdma_clr_bits(dmadev, reg, STM32_MDMA_CCR_EN);
422 				dmadev->base + STM32_MDMA_CISR(id), cisr,
435 	struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
445 	status = stm32_mdma_read(dmadev, STM32_MDMA_CISR(chan->id));
449 		stm32_mdma_set_bits(dmadev, STM32_MDMA_CIFCR(chan->id), status);
455 static void stm32_mdma_set_bus(struct stm32_mdma_device *dmadev, u32 *ctbr,
464 	for (i = 0; i < dmadev->nr_ahb_addr_masks; i++) {
465 		if (mask == dmadev->ahb_addr_masks[i]) {
478 	struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
491 	ccr = stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id)) & ~STM32_MDMA_CCR_EN;
492 	ctcr = stm32_mdma_read(dmadev, STM32_MDMA_CTCR(chan->id));
493 	ctbr = stm32_mdma_read(dmadev, STM32_MDMA_CTBR(chan->id));
592 		stm32_mdma_set_bus(dmadev, &ctbr, STM32_MDMA_CTBR_DBUS,
599 		stm32_mdma_write(dmadev, STM32_MDMA_CDAR(chan->id), dst_addr);
650 		stm32_mdma_set_bus(dmadev, &ctbr, STM32_MDMA_CTBR_SBUS,
657 		stm32_mdma_write(dmadev, STM32_MDMA_CSAR(chan->id), src_addr);
729 	struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
754 			stm32_mdma_set_bus(dmadev, &ctbr, STM32_MDMA_CTBR_SBUS,
764 			stm32_mdma_set_bus(dmadev, &ctbr, STM32_MDMA_CTBR_DBUS,
847 	struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
887 		stm32_mdma_set_bus(dmadev, &ctbr, STM32_MDMA_CTBR_SBUS,
893 		stm32_mdma_set_bus(dmadev, &ctbr, STM32_MDMA_CTBR_DBUS,
941 	struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
967 	ccr = stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id)) & ~STM32_MDMA_CCR_EN;
968 	ctcr = stm32_mdma_read(dmadev, STM32_MDMA_CTCR(chan->id));
969 	ctbr = stm32_mdma_read(dmadev, STM32_MDMA_CTBR(chan->id));
970 	cbndtr = stm32_mdma_read(dmadev, STM32_MDMA_CBNDTR(chan->id));
993 	stm32_mdma_set_bus(dmadev, &ctbr, STM32_MDMA_CTBR_SBUS, src);
994 	stm32_mdma_set_bus(dmadev, &ctbr, STM32_MDMA_CTBR_DBUS, dest);
1117 	struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
1120 		stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id)));
1122 		stm32_mdma_read(dmadev, STM32_MDMA_CTCR(chan->id)));
1124 		stm32_mdma_read(dmadev, STM32_MDMA_CBNDTR(chan->id)));
1126 		stm32_mdma_read(dmadev, STM32_MDMA_CSAR(chan->id)));
1128 		stm32_mdma_read(dmadev, STM32_MDMA_CDAR(chan->id)));
1130 		stm32_mdma_read(dmadev, STM32_MDMA_CBRUR(chan->id)));
1132 		stm32_mdma_read(dmadev, STM32_MDMA_CLAR(chan->id)));
1134 		stm32_mdma_read(dmadev, STM32_MDMA_CTBR(chan->id)));
1136 		stm32_mdma_read(dmadev, STM32_MDMA_CMAR(chan->id)));
1138 		stm32_mdma_read(dmadev, STM32_MDMA_CMDR(chan->id)));
1143 	struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
1161 	stm32_mdma_write(dmadev, STM32_MDMA_CCR(id), chan->desc->ccr);
1162 	stm32_mdma_write(dmadev, STM32_MDMA_CTCR(id), hwdesc->ctcr);
1163 	stm32_mdma_write(dmadev, STM32_MDMA_CBNDTR(id), hwdesc->cbndtr);
1164 	stm32_mdma_write(dmadev, STM32_MDMA_CSAR(id), hwdesc->csar);
1165 	stm32_mdma_write(dmadev, STM32_MDMA_CDAR(id), hwdesc->cdar);
1166 	stm32_mdma_write(dmadev, STM32_MDMA_CBRUR(id), hwdesc->cbrur);
1167 	stm32_mdma_write(dmadev, STM32_MDMA_CLAR(id), hwdesc->clar);
1168 	stm32_mdma_write(dmadev, STM32_MDMA_CTBR(id), hwdesc->ctbr);
1169 	stm32_mdma_write(dmadev, STM32_MDMA_CMAR(id), hwdesc->cmar);
1170 	stm32_mdma_write(dmadev, STM32_MDMA_CMDR(id), hwdesc->cmdr);
1173 	status = stm32_mdma_read(dmadev, STM32_MDMA_CISR(id));
1175 		stm32_mdma_set_bits(dmadev, STM32_MDMA_CIFCR(id), status);
1180 	stm32_mdma_set_bits(dmadev, STM32_MDMA_CCR(id), STM32_MDMA_CCR_EN);
1185 		stm32_mdma_set_bits(dmadev, reg, STM32_MDMA_CCR_SWRQ);
1231 	struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
1237 	if (!chan->desc || (stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id)) & STM32_MDMA_CCR_EN))
1245 	stm32_mdma_write(dmadev, STM32_MDMA_CCR(chan->id), chan->desc->ccr);
1248 	status = stm32_mdma_read(dmadev, STM32_MDMA_CISR(chan->id));
1250 		stm32_mdma_set_bits(dmadev, STM32_MDMA_CIFCR(chan->id), status);
1256 	stm32_mdma_set_bits(dmadev, reg, STM32_MDMA_CCR_EN);
1260 		stm32_mdma_set_bits(dmadev, reg, STM32_MDMA_CCR_SWRQ);
1323 	struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
1328 	cisr = stm32_mdma_read(dmadev, STM32_MDMA_CISR(chan->id));
1332 	clar = stm32_mdma_read(dmadev, STM32_MDMA_CLAR(chan->id));
1342 	cbndtr = stm32_mdma_read(dmadev, STM32_MDMA_CBNDTR(chan->id));
1401 	struct stm32_mdma_device *dmadev = devid;
1406 	status = readl_relaxed(dmadev->base + STM32_MDMA_GISR0);
1408 		dev_dbg(mdma2dev(dmadev), "spurious it\n");
1412 	chan = &dmadev->chan[id];
1416 	status = stm32_mdma_read(dmadev, STM32_MDMA_CISR(id));
1419 	ccr = stm32_mdma_read(dmadev, STM32_MDMA_CCR(id));
1437 			readl_relaxed(dmadev->base + STM32_MDMA_CESR(id)));
1438 		stm32_mdma_set_bits(dmadev, reg, STM32_MDMA_CIFCR_CTEIF);
1443 		stm32_mdma_set_bits(dmadev, reg, STM32_MDMA_CIFCR_CCTCIF);
1449 		stm32_mdma_set_bits(dmadev, reg, STM32_MDMA_CIFCR_CBRTIF);
1454 		stm32_mdma_set_bits(dmadev, reg, STM32_MDMA_CIFCR_CBTIF);
1465 		stm32_mdma_set_bits(dmadev, reg, STM32_MDMA_CIFCR_CLTCIF);
1470 		stm32_mdma_set_bits(dmadev, reg, status);
1484 	struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
1497 	ret = pm_runtime_resume_and_get(dmadev->ddev.dev);
1503 		pm_runtime_put(dmadev->ddev.dev);
1511 	struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
1523 	pm_runtime_put(dmadev->ddev.dev);
1532 	struct stm32_mdma_device *dmadev = stm32_mdma_get_dev(chan);
1535 	if (dmadev->chan_reserved & BIT(chan->id))
1544 	struct stm32_mdma_device *dmadev = ofdma->of_dma_data;
1545 	dma_cap_mask_t mask = dmadev->ddev.cap_mask;
1551 		dev_err(mdma2dev(dmadev), "Bad number of args\n");
1562 	if (config.request >= dmadev->nr_requests) {
1563 		dev_err(mdma2dev(dmadev), "Bad request line\n");
1568 		dev_err(mdma2dev(dmadev), "Priority level not supported\n");
1574 		dev_err(mdma2dev(dmadev), "No more channels available\n");
1593 	struct stm32_mdma_device *dmadev;
1624 	dmadev = devm_kzalloc(&pdev->dev,
1625 			      struct_size(dmadev, ahb_addr_masks, count),
1627 	if (!dmadev)
1629 	dmadev->nr_ahb_addr_masks = count;
1631 	dmadev->nr_channels = nr_channels;
1632 	dmadev->nr_requests = nr_requests;
1634 				       dmadev->ahb_addr_masks,
1637 	dmadev->base = devm_platform_ioremap_resource(pdev, 0);
1638 	if (IS_ERR(dmadev->base))
1639 		return PTR_ERR(dmadev->base);
1641 	dmadev->clk = devm_clk_get(&pdev->dev, NULL);
1642 	if (IS_ERR(dmadev->clk))
1643 		return dev_err_probe(&pdev->dev, PTR_ERR(dmadev->clk),
1646 	ret = clk_prepare_enable(dmadev->clk);
1663 	dd = &dmadev->ddev;
1697 	for (i = 0; i < dmadev->nr_channels; i++) {
1698 		chan = &dmadev->chan[i];
1701 		if (stm32_mdma_read(dmadev, STM32_MDMA_CCR(i)) & STM32_MDMA_CCR_SM)
1702 			dmadev->chan_reserved |= BIT(i);
1708 	dmadev->irq = platform_get_irq(pdev, 0);
1709 	if (dmadev->irq < 0) {
1710 		ret = dmadev->irq;
1714 	ret = devm_request_irq(&pdev->dev, dmadev->irq, stm32_mdma_irq_handler,
1715 			       0, dev_name(&pdev->dev), dmadev);
1725 	ret = of_dma_controller_register(of_node, stm32_mdma_of_xlate, dmadev);
1732 	platform_set_drvdata(pdev, dmadev);
1743 	clk_disable_unprepare(dmadev->clk);
1751 	struct stm32_mdma_device *dmadev = dev_get_drvdata(dev);
1753 	clk_disable_unprepare(dmadev->clk);
1760 	struct stm32_mdma_device *dmadev = dev_get_drvdata(dev);
1763 	ret = clk_prepare_enable(dmadev->clk);
1776 	struct stm32_mdma_device *dmadev = dev_get_drvdata(dev);
1784 	for (id = 0; id < dmadev->nr_channels; id++) {
1785 		ccr = stm32_mdma_read(dmadev, STM32_MDMA_CCR(id));