dma/sh/rz-dmac.c

175 static void rz_dmac_writel(struct rz_dmac *dmac, unsigned int val,
178 	writel(val, dmac->base + offset);
181 static void rz_dmac_ext_writel(struct rz_dmac *dmac, unsigned int val,
184 	writel(val, dmac->ext_base + offset);
187 static u32 rz_dmac_ext_readl(struct rz_dmac *dmac, unsigned int offset)
189 	return readl(dmac->ext_base + offset);
256 	struct rz_dmac *dmac = to_rz_dmac(chan->device);
262 	dev_dbg(dmac->dev, "%s channel %d\n", __func__, channel->index);
287 	struct rz_dmac *dmac = to_rz_dmac(chan->device);
290 	dev_dbg(dmac->dev, "%s channel %d\n", __func__, channel->index);
297 static void rz_dmac_set_dmars_register(struct rz_dmac *dmac, int nr, u32 dmars)
303 	dmars32 = rz_dmac_ext_readl(dmac, dmars_offset);
307 	rz_dmac_ext_writel(dmac, dmars32, dmars_offset);
313 	struct rz_dmac *dmac = to_rz_dmac(chan->device);
327 	rz_dmac_set_dmars_register(dmac, channel->index, 0);
336 	struct rz_dmac *dmac = to_rz_dmac(chan->device);
378 	rz_dmac_set_dmars_register(dmac, channel->index, channel->mid_rid);
440 	struct rz_dmac *dmac = to_rz_dmac(chan->device);
456 		clear_bit(channel->mid_rid, dmac->modules);
476 	struct rz_dmac *dmac = to_rz_dmac(chan->device);
479 	dev_dbg(dmac->dev, "%s channel: %d src=0x%pad dst=0x%pad len=%zu\n",
553 	struct rz_dmac *dmac = to_rz_dmac(chan->device);
565 				dev_warn(dmac->dev, "ch: %d couldn't issue DMA xfer\n",
638 	struct rz_dmac *dmac = to_rz_dmac(chan->device);
645 		dev_warn(dmac->dev, "DMA Timeout");
647 	rz_dmac_set_dmars_register(dmac, channel->index, 0);
658 	struct rz_dmac *dmac = to_rz_dmac(chan->device);
663 		dev_err(dmac->dev, "DMAC err CHSTAT_%d = %08X\n",
724 	struct rz_dmac *dmac = to_rz_dmac(chan->device);
733 	return !test_and_set_bit(channel->mid_rid, dmac->modules);
756 static int rz_dmac_chan_probe(struct rz_dmac *dmac,
760 	struct platform_device *pdev = to_platform_device(dmac->dev);
775 	irqname = devm_kasprintf(dmac->dev, GFP_KERNEL, "%s:%u",
776 				 dev_name(dmac->dev), index);
780 	ret = devm_request_threaded_irq(dmac->dev, channel->irq,
785 		dev_err(dmac->dev, "failed to request IRQ %u (%d)\n",
792 		channel->ch_base = dmac->base + CHANNEL_0_7_OFFSET +
794 		channel->ch_cmn_base = dmac->base + CHANNEL_0_7_COMMON_BASE;
796 		channel->ch_base = dmac->base + CHANNEL_8_15_OFFSET +
798 		channel->ch_cmn_base = dmac->base + CHANNEL_8_15_COMMON_BASE;
815 	vchan_init(&channel->vc, &dmac->engine);
823 static int rz_dmac_parse_of(struct device *dev, struct rz_dmac *dmac)
828 	ret = of_property_read_u32(np, "dma-channels", &dmac->n_channels);
834 	if (!dmac->n_channels || dmac->n_channels > RZ_DMAC_MAX_CHANNELS) {
835 		dev_err(dev, "invalid number of channels %u\n", dmac->n_channels);
846 	struct rz_dmac *dmac;
852 	dmac = devm_kzalloc(&pdev->dev, sizeof(*dmac), GFP_KERNEL);
853 	if (!dmac)
856 	dmac->dev = &pdev->dev;
857 	platform_set_drvdata(pdev, dmac);
859 	ret = rz_dmac_parse_of(&pdev->dev, dmac);
863 	dmac->channels = devm_kcalloc(&pdev->dev, dmac->n_channels,
864 				      sizeof(*dmac->channels), GFP_KERNEL);
865 	if (!dmac->channels)
869 	dmac->base = devm_platform_ioremap_resource(pdev, 0);
870 	if (IS_ERR(dmac->base))
871 		return PTR_ERR(dmac->base);
873 	dmac->ext_base = devm_platform_ioremap_resource(pdev, 1);
874 	if (IS_ERR(dmac->ext_base))
875 		return PTR_ERR(dmac->ext_base);
891 	INIT_LIST_HEAD(&dmac->engine.channels);
893 	dmac->rstc = devm_reset_control_array_get_exclusive(&pdev->dev);
894 	if (IS_ERR(dmac->rstc))
895 		return dev_err_probe(&pdev->dev, PTR_ERR(dmac->rstc),
905 	ret = reset_control_deassert(dmac->rstc);
909 	for (i = 0; i < dmac->n_channels; i++) {
910 		ret = rz_dmac_chan_probe(dmac, &dmac->channels[i], i);
922 	engine = &dmac->engine;
925 	rz_dmac_writel(dmac, DCTRL_DEFAULT, CHANNEL_0_7_COMMON_BASE + DCTRL);
926 	rz_dmac_writel(dmac, DCTRL_DEFAULT, CHANNEL_8_15_COMMON_BASE + DCTRL);
955 		struct rz_dmac_chan *channel = &dmac->channels[i];
963 	reset_control_assert(dmac->rstc);
974 	struct rz_dmac *dmac = platform_get_drvdata(pdev);
977 	dma_async_device_unregister(&dmac->engine);
979 	for (i = 0; i < dmac->n_channels; i++) {
980 		struct rz_dmac_chan *channel = &dmac->channels[i];
987 	reset_control_assert(dmac->rstc);
993 	{ .compatible = "renesas,rz-dmac", },
1000 		.name	= "rz-dmac",