dma/ptdma/ptdma-dev.c

57 void pt_start_queue(struct pt_cmd_queue *cmd_q)
60 	iowrite32(cmd_q->qcontrol | CMD_Q_RUN, cmd_q->reg_control);
63 void pt_stop_queue(struct pt_cmd_queue *cmd_q)
66 	iowrite32(cmd_q->qcontrol & ~CMD_Q_RUN, cmd_q->reg_control);
69 static int pt_core_execute_cmd(struct ptdma_desc *desc, struct pt_cmd_queue *cmd_q)
72 	u8 *q_desc = (u8 *)&cmd_q->qbase[cmd_q->qidx];
80 	spin_lock_irqsave(&cmd_q->q_lock, flags);
84 	cmd_q->qidx = (cmd_q->qidx + 1) % CMD_Q_LEN;
90 	tail = lower_32_bits(cmd_q->qdma_tail + cmd_q->qidx * Q_DESC_SIZE);
91 	iowrite32(tail, cmd_q->reg_control + 0x0004);
94 	pt_start_queue(cmd_q);
95 	spin_unlock_irqrestore(&cmd_q->q_lock, flags);
100 int pt_core_perform_passthru(struct pt_cmd_queue *cmd_q,
104 	struct pt_device *pt = container_of(cmd_q, struct pt_device, cmd_q);
106 	cmd_q->cmd_error = 0;
107 	cmd_q->total_pt_ops++;
116 	if (cmd_q->int_en)
121 	return pt_core_execute_cmd(&desc, cmd_q);
128 	struct pt_cmd_queue *cmd_q = &cmd->pt->cmd_q;
131 	if (cmd_q->cmd_error) {
136 		tail = lower_32_bits(cmd_q->qdma_tail + cmd_q->qidx * Q_DESC_SIZE);
137 		pt_log_error(cmd_q->pt, cmd_q->cmd_error);
138 		iowrite32(tail, cmd_q->reg_control + 0x0008);
144 void pt_check_status_trans(struct pt_device *pt, struct pt_cmd_queue *cmd_q)
148 	status = ioread32(cmd_q->reg_control + 0x0010);
150 		cmd_q->int_status = status;
151 		cmd_q->q_status = ioread32(cmd_q->reg_control + 0x0100);
152 		cmd_q->q_int_status = ioread32(cmd_q->reg_control + 0x0104);
155 		if ((status & INT_ERROR) && !cmd_q->cmd_error)
156 			cmd_q->cmd_error = CMD_Q_ERROR(cmd_q->q_status);
159 		iowrite32(status, cmd_q->reg_control + 0x0010);
167 	struct pt_cmd_queue *cmd_q = &pt->cmd_q;
171 	pt_check_status_trans(pt, cmd_q);
179 	struct pt_cmd_queue *cmd_q = &pt->cmd_q;
201 	cmd_q->pt = pt;
202 	cmd_q->dma_pool = dma_pool;
203 	spin_lock_init(&cmd_q->q_lock);
206 	cmd_q->qsize = Q_SIZE(Q_DESC_SIZE);
207 	cmd_q->qbase = dma_alloc_coherent(dev, cmd_q->qsize,
208 					  &cmd_q->qbase_dma,
210 	if (!cmd_q->qbase) {
216 	cmd_q->qidx = 0;
219 	cmd_q->reg_control = pt->io_regs + CMD_Q_STATUS_INCR;
224 	cmd_q->qcontrol = 0; /* Start with nothing */
225 	iowrite32(cmd_q->qcontrol, cmd_q->reg_control);
227 	ioread32(cmd_q->reg_control + 0x0104);
228 	ioread32(cmd_q->reg_control + 0x0100);
231 	iowrite32(SUPPORTED_INTERRUPTS, cmd_q->reg_control + 0x0010);
241 	cmd_q->qcontrol &= ~CMD_Q_SIZE;
242 	cmd_q->qcontrol |= FIELD_PREP(CMD_Q_SIZE, QUEUE_SIZE_VAL);
244 	cmd_q->qdma_tail = cmd_q->qbase_dma;
245 	dma_addr_lo = lower_32_bits(cmd_q->qdma_tail);
246 	iowrite32((u32)dma_addr_lo, cmd_q->reg_control + 0x0004);
247 	iowrite32((u32)dma_addr_lo, cmd_q->reg_control + 0x0008);
249 	dma_addr_hi = upper_32_bits(cmd_q->qdma_tail);
250 	cmd_q->qcontrol |= (dma_addr_hi << 16);
251 	iowrite32(cmd_q->qcontrol, cmd_q->reg_control);
269 	dma_free_coherent(dev, cmd_q->qsize, cmd_q->qbase, cmd_q->qbase_dma);
272 	dma_pool_destroy(pt->cmd_q.dma_pool);
280 	struct pt_cmd_queue *cmd_q = &pt->cmd_q;
290 	pt_stop_queue(cmd_q);
293 	iowrite32(SUPPORTED_INTERRUPTS, cmd_q->reg_control + 0x0010);
294 	ioread32(cmd_q->reg_control + 0x0104);
295 	ioread32(cmd_q->reg_control + 0x0100);
299 	dma_free_coherent(dev, cmd_q->qsize, cmd_q->qbase,
300 			  cmd_q->qbase_dma);