drivers/dma/pl330.c

719 		enum dmamov_dst dst, u32 val)
726 	buf[2] = val;
727 	buf[3] = val >> 8;
728 	buf[4] = val >> 16;
729 	buf[5] = val >> 24;
732 		dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val);
894 	u32 val;
902 	val = (insn[0] << 16) | (insn[1] << 24);
904 		val |= (1 << 0);
905 		val |= (thrd->id << 8); /* Channel Number */
907 	writel(val, regs + DBGINST0);
909 	val = le32_to_cpu(*((__le32 *)&insn[2]));
910 	writel(val, regs + DBGINST1);
919 	u32 val;
922 		val = readl(regs + DS) & 0xf;
924 		val = readl(regs + CS(thrd->id)) & 0xf;
926 	switch (val) {
1644 	u32 val;
1651 	val = readl(regs + FSM) & 0x1;
1652 	if (val)
1657 	val = readl(regs + FSC) & ((1 << pl330->pcfg.num_chan) - 1);
1658 	pl330->dmac_tbd.reset_chan |= val;
1659 	if (val) {
1662 			if (val & (1 << i)) {
1674 	val = readl(regs + ES);
1676 			&& val & ~((1 << pl330->pcfg.num_events) - 1)) {
1685 		if (val & (1 << ev)) { /* Event occurred */
1825 	u32 val;
1827 	val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT;
1828 	val &= CRD_DATA_WIDTH_MASK;
1829 	pl330->pcfg.data_bus_width = 8 * (1 << val);
1831 	val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT;
1832 	val &= CRD_DATA_BUFF_MASK;
1833 	pl330->pcfg.data_buf_dep = val + 1;
1835 	val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT;
1836 	val &= CR0_NUM_CHANS_MASK;
1837 	val += 1;
1838 	pl330->pcfg.num_chan = val;
1840 	val = readl(regs + CR0);
1841 	if (val & CR0_PERIPH_REQ_SET) {
1842 		val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK;
1843 		val += 1;
1844 		pl330->pcfg.num_peri = val;
1850 	val = readl(regs + CR0);
1851 	if (val & CR0_BOOT_MAN_NS)
1856 	val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT;
1857 	val &= CR0_NUM_EVENTS_MASK;
1858 	val += 1;
1859 	pl330->pcfg.num_events = val;
2385 	u32 val, addr;
2388 	val = addr = 0;
2390 		val = readl(regs + SA(thrd->id));
2393 		val = readl(regs + DA(thrd->id));
2400 	if (!val)
2403 	return val - addr;