drivers/dma/moxart-dma.c

185 	struct moxart_chan *ch = to_moxart_dma_chan(chan);
190 	dev_dbg(chan2dev(chan), "%s: ch=%p\n", __func__, ch);
192 	spin_lock_irqsave(&ch->vc.lock, flags);
194 	if (ch->desc) {
195 		moxart_dma_desc_free(&ch->desc->vd);
196 		ch->desc = NULL;
199 	ctrl = readl(ch->base + REG_OFF_CTRL);
201 	writel(ctrl, ch->base + REG_OFF_CTRL);
203 	vchan_get_all_descriptors(&ch->vc, &head);
204 	spin_unlock_irqrestore(&ch->vc.lock, flags);
205 	vchan_dma_desc_free_list(&ch->vc, &head);
213 	struct moxart_chan *ch = to_moxart_dma_chan(chan);
216 	ch->cfg = *cfg;
218 	ctrl = readl(ch->base + REG_OFF_CTRL);
223 	switch (ch->cfg.src_addr_width) {
226 		if (ch->cfg.direction != DMA_MEM_TO_DEV)
233 		if (ch->cfg.direction != DMA_MEM_TO_DEV)
240 		if (ch->cfg.direction != DMA_MEM_TO_DEV)
249 	if (ch->cfg.direction == DMA_MEM_TO_DEV) {
252 		ctrl |= (ch->line_reqno << 16 &
257 		ctrl |= (ch->line_reqno << 24 &
261 	writel(ctrl, ch->base + REG_OFF_CTRL);
271 	struct moxart_chan *ch = to_moxart_dma_chan(chan);
286 		dev_addr = ch->cfg.src_addr;
287 		dev_width = ch->cfg.src_addr_width;
289 		dev_addr = ch->cfg.dst_addr;
290 		dev_width = ch->cfg.dst_addr_width;
323 	ch->error = 0;
325 	return vchan_tx_prep(&ch->vc, &d->vd, tx_flags);
333 	struct moxart_chan *ch;
339 	ch = to_moxart_dma_chan(chan);
340 	ch->line_reqno = dma_spec->args[0];
347 	struct moxart_chan *ch = to_moxart_dma_chan(chan);
350 		__func__, ch->ch_num);
351 	ch->allocated = 1;
358 	struct moxart_chan *ch = to_moxart_dma_chan(chan);
360 	vchan_free_chan_resources(&ch->vc);
363 		__func__, ch->ch_num);
364 	ch->allocated = 0;
367 static void moxart_dma_set_params(struct moxart_chan *ch, dma_addr_t src_addr,
370 	writel(src_addr, ch->base + REG_OFF_ADDRESS_SOURCE);
371 	writel(dst_addr, ch->base + REG_OFF_ADDRESS_DEST);
374 static void moxart_set_transfer_params(struct moxart_chan *ch, unsigned int len)
376 	struct moxart_desc *d = ch->desc;
385 	writel(d->dma_cycles, ch->base + REG_OFF_CYCLES);
387 	dev_dbg(chan2dev(&ch->vc.chan), "%s: set %u DMA cycles (len=%u)\n",
391 static void moxart_start_dma(struct moxart_chan *ch)
395 	ctrl = readl(ch->base + REG_OFF_CTRL);
397 	writel(ctrl, ch->base + REG_OFF_CTRL);
400 static void moxart_dma_start_sg(struct moxart_chan *ch, unsigned int idx)
402 	struct moxart_desc *d = ch->desc;
403 	struct moxart_sg *sg = ch->desc->sg + idx;
405 	if (ch->desc->dma_dir == DMA_MEM_TO_DEV)
406 		moxart_dma_set_params(ch, sg->addr, d->dev_addr);
407 	else if (ch->desc->dma_dir == DMA_DEV_TO_MEM)
408 		moxart_dma_set_params(ch, d->dev_addr, sg->addr);
410 	moxart_set_transfer_params(ch, sg->len);
412 	moxart_start_dma(ch);
417 	struct moxart_chan *ch = to_moxart_dma_chan(chan);
420 	vd = vchan_next_desc(&ch->vc);
423 		ch->desc = NULL;
429 	ch->desc = to_moxart_dma_desc(&vd->tx);
430 	ch->sgidx = 0;
432 	moxart_dma_start_sg(ch, 0);
437 	struct moxart_chan *ch = to_moxart_dma_chan(chan);
440 	spin_lock_irqsave(&ch->vc.lock, flags);
441 	if (vchan_issue_pending(&ch->vc) && !ch->desc)
443 	spin_unlock_irqrestore(&ch->vc.lock, flags);
458 static size_t moxart_dma_desc_size_in_flight(struct moxart_chan *ch)
463 	size = moxart_dma_desc_size(ch->desc, ch->sgidx);
464 	cycles = readl(ch->base + REG_OFF_CYCLES);
465 	completed_cycles = (ch->desc->dma_cycles - cycles);
466 	size -= completed_cycles << es_bytes[ch->desc->es];
468 	dev_dbg(chan2dev(&ch->vc.chan), "%s: size=%zu\n", __func__, size);
477 	struct moxart_chan *ch = to_moxart_dma_chan(chan);
488 	spin_lock_irqsave(&ch->vc.lock, flags);
489 	vd = vchan_find_desc(&ch->vc, cookie);
493 	} else if (ch->desc && ch->desc->vd.tx.cookie == cookie) {
494 		txstate->residue = moxart_dma_desc_size_in_flight(ch);
496 	spin_unlock_irqrestore(&ch->vc.lock, flags);
498 	if (ch->error)
521 	struct moxart_chan *ch = &mc->slave_chans[0];
525 	dev_dbg(chan2dev(&ch->vc.chan), "%s\n", __func__);
527 	for (i = 0; i < APB_DMA_MAX_CHANNEL; i++, ch++) {
528 		if (!ch->allocated)
531 		ctrl = readl(ch->base + REG_OFF_CTRL);
533 		dev_dbg(chan2dev(&ch->vc.chan), "%s: ch=%p ch->base=%p ctrl=%x\n",
534 			__func__, ch, ch->base, ctrl);
538 			if (ch->desc) {
539 				spin_lock(&ch->vc.lock);
540 				if (++ch->sgidx < ch->desc->sglen) {
541 					moxart_dma_start_sg(ch, ch->sgidx);
543 					vchan_cookie_complete(&ch->desc->vd);
544 					moxart_dma_start_desc(&ch->vc.chan);
546 				spin_unlock(&ch->vc.lock);
552 			ch->error = 1;
555 		writel(ctrl, ch->base + REG_OFF_CTRL);
568 	struct moxart_chan *ch;
591 	ch = &mdc->slave_chans[0];
592 	for (i = 0; i < APB_DMA_MAX_CHANNEL; i++, ch++) {
593 		ch->ch_num = i;
594 		ch->base = dma_base_addr + i * REG_OFF_CHAN_SIZE;
595 		ch->allocated = 0;
597 		ch->vc.desc_free = moxart_dma_desc_free;
598 		vchan_init(&ch->vc, &mdc->dma_slave);
600 		dev_dbg(dev, "%s: chs[%d]: ch->ch_num=%u ch->base=%p\n",
601 			__func__, i, ch->ch_num, ch->base);