Lines Matching defs:sdma
3 // drivers/dma/imx-sdma.c
314 * struct sdma_context_data - sdma context specific to a channel
401 * @desc: sdma description including vd and other special member
402 * @sdma: pointer to the SDMA engine for this channel
424 * @data: specific sdma interface structure
438 struct sdma_engine *sdma;
504 * ecspi ERR009165 fixed should be done in sdma script
663 { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, },
664 { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, },
665 { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, },
666 { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, },
667 { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
668 { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
669 { .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, },
670 { .compatible = "fsl,imx6ul-sdma", .data = &sdma_imx6ul, },
671 { .compatible = "fsl,imx8mq-sdma", .data = &sdma_imx8mq, },
681 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
683 u32 chnenbl0 = sdma->drvdata->chnenbl0;
690 struct sdma_engine *sdma = sdmac->sdma;
697 evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR);
698 mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR);
699 dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR);
716 writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR);
717 writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR);
718 writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR);
723 static int is_sdma_channel_enabled(struct sdma_engine *sdma, int channel)
725 return !!(readl(sdma->regs + SDMA_H_STATSTOP) & BIT(channel));
728 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
730 writel(BIT(channel), sdma->regs + SDMA_H_START);
736 static int sdma_run_channel0(struct sdma_engine *sdma)
741 sdma_enable_channel(sdma, 0);
743 ret = readl_relaxed_poll_timeout_atomic(sdma->regs + SDMA_H_STATSTOP,
746 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
749 reg = readl(sdma->regs + SDMA_H_CONFIG);
752 writel_relaxed(reg, sdma->regs + SDMA_H_CONFIG);
758 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
761 struct sdma_buffer_descriptor *bd0 = sdma->bd0;
767 buf_virt = dma_alloc_coherent(sdma->dev, size, &buf_phys, GFP_KERNEL);
771 spin_lock_irqsave(&sdma->channel_0_lock, flags);
781 ret = sdma_run_channel0(sdma);
783 spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
785 dma_free_coherent(sdma->dev, size, buf_virt, buf_phys);
792 struct sdma_engine *sdma = sdmac->sdma;
795 u32 chnenbl = chnenbl_ofs(sdma, event);
797 val = readl_relaxed(sdma->regs + chnenbl);
799 writel_relaxed(val, sdma->regs + chnenbl);
803 val = readl_relaxed(sdma->regs + SDMA_DONE0_CONFIG);
806 writel_relaxed(val, sdma->regs + SDMA_DONE0_CONFIG);
812 struct sdma_engine *sdma = sdmac->sdma;
814 u32 chnenbl = chnenbl_ofs(sdma, event);
817 val = readl_relaxed(sdma->regs + chnenbl);
819 writel_relaxed(val, sdma->regs + chnenbl);
831 struct sdma_engine *sdma = sdmac->sdma;
842 sdma->channel_control[channel].base_bd_ptr = desc->bd_phys;
843 sdma->channel_control[channel].current_bd_ptr = desc->bd_phys;
844 sdma_enable_channel(sdma, sdmac->channel);
902 if (sdmac->desc && !is_sdma_channel_enabled(sdmac->sdma, sdmac->channel)) {
903 dev_warn(sdmac->sdma->dev, "restart cyclic channel %d\n", sdmac->channel);
904 sdma_enable_channel(sdmac->sdma, sdmac->channel);
935 struct sdma_engine *sdma = dev_id;
938 stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
939 writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
945 struct sdma_channel *sdmac = &sdma->channel[channel];
976 struct sdma_engine *sdma = sdmac->sdma;
992 emi_2_emi = sdma->script_addrs->ap_2_ap_addr;
995 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
996 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
999 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
1000 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
1003 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
1004 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
1007 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
1008 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
1011 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
1012 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
1015 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
1018 if (sdmac->sdma->drvdata->ecspi_fixed) {
1019 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
1021 emi_2_per = sdma->script_addrs->mcu_2_ecspi_addr;
1029 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
1030 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
1033 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr;
1034 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr;
1043 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
1044 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
1047 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
1048 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
1049 per_2_per = sdma->script_addrs->per_2_per_addr;
1053 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
1054 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
1055 per_2_per = sdma->script_addrs->per_2_per_addr;
1058 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
1059 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
1062 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
1065 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
1066 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
1069 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
1072 per_2_emi = sdma->script_addrs->sai_2_mcu_addr;
1073 emi_2_per = sdma->script_addrs->mcu_2_sai_addr;
1076 emi_2_per = sdma->script_addrs->hdmi_dma_addr;
1080 dev_err(sdma->dev, "Unsupported transfer type %d\n",
1095 struct sdma_engine *sdma = sdmac->sdma;
1098 struct sdma_context_data *context = sdma->context;
1099 struct sdma_buffer_descriptor *bd0 = sdma->bd0;
1115 dev_dbg(sdma->dev, "load_address = %d\n", load_address);
1116 dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level);
1117 dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
1118 dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
1119 dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]);
1120 dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]);
1122 spin_lock_irqsave(&sdma->channel_0_lock, flags);
1144 bd0->buffer_addr = sdma->context_phys;
1146 ret = sdma_run_channel0(sdma);
1148 spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
1161 struct sdma_engine *sdma = sdmac->sdma;
1164 writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
1222 struct sdma_engine *sdma = sdmac->sdma;
1249 if (sdmac->per_address2 >= sdma->spba_start_addr &&
1250 sdmac->per_address2 <= sdma->spba_end_addr)
1253 if (sdmac->per_address >= sdma->spba_start_addr &&
1254 sdmac->per_address <= sdma->spba_end_addr)
1344 struct sdma_engine *sdma = sdmac->sdma;
1352 writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
1357 static int sdma_request_channel0(struct sdma_engine *sdma)
1361 sdma->bd0 = dma_alloc_coherent(sdma->dev, PAGE_SIZE, &sdma->bd0_phys,
1363 if (!sdma->bd0) {
1368 sdma->channel_control[0].base_bd_ptr = sdma->bd0_phys;
1369 sdma->channel_control[0].current_bd_ptr = sdma->bd0_phys;
1371 sdma_set_channel_priority(&sdma->channel[0], MXC_SDMA_DEFAULT_PRIORITY);
1384 desc->bd = dma_alloc_coherent(desc->sdmac->sdma->dev, bd_size,
1398 dma_free_coherent(desc->sdmac->sdma->dev, bd_size, desc->bd,
1427 dev_dbg(sdmac->sdma->dev, "MEMCPY in case?\n");
1456 ret = clk_enable(sdmac->sdma->clk_ipg);
1459 ret = clk_enable(sdmac->sdma->clk_ahb);
1470 clk_disable(sdmac->sdma->clk_ahb);
1472 clk_disable(sdmac->sdma->clk_ipg);
1479 struct sdma_engine *sdma = sdmac->sdma;
1494 clk_disable(sdma->clk_ipg);
1495 clk_disable(sdma->clk_ahb);
1503 if (!sdmac->sdma->fw_loaded && sdmac->is_ram_script) {
1504 dev_warn_once(sdmac->sdma->dev, "sdma firmware not ready!\n");
1548 struct sdma_engine *sdma = sdmac->sdma;
1558 dev_dbg(sdma->dev, "memcpy: %pad->%pad, len=%zu, channel=%d.\n",
1588 dev_dbg(sdma->dev, "entry %d: count: %zd dma: 0x%x %s%s\n",
1605 struct sdma_engine *sdma = sdmac->sdma;
1617 dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
1629 dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
1666 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
1689 struct sdma_engine *sdma = sdmac->sdma;
1695 dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
1711 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %zu > %d\n",
1738 dev_dbg(sdma->dev, "entry %d: count: %zu dma: %#llx %s%s\n",
1797 struct sdma_engine *sdma = sdmac->sdma;
1804 dev_err(sdma->dev, "Invalid peripheral size %zu, expected %zu\n",
1818 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
1823 if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events)
1888 static void sdma_add_scripts(struct sdma_engine *sdma,
1892 s32 *saddr_arr = (u32 *)sdma->script_addrs;
1896 if (!sdma->script_number)
1897 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1899 if (sdma->script_number > sizeof(struct sdma_script_start_addrs)
1901 dev_err(sdma->dev,
1903 sdma->script_number);
1907 for (i = 0; i < sdma->script_number; i++)
1914 * script, both uart ram/rom scripts are present in newer sdma
1917 if (sdma->script_number >= SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3) {
1919 sdma->script_addrs->uart_2_mcu_addr = addr->uart_2_mcu_rom_addr;
1921 sdma->script_addrs->uartsh_2_mcu_addr = addr->uartsh_2_mcu_rom_addr;
1927 struct sdma_engine *sdma = context;
1933 dev_info(sdma->dev, "external firmware not found, using ROM firmware\n");
1949 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1952 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2;
1955 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3;
1958 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4;
1961 dev_err(sdma->dev, "unknown firmware version\n");
1968 clk_enable(sdma->clk_ipg);
1969 clk_enable(sdma->clk_ahb);
1971 sdma_load_script(sdma, ram_code,
1974 clk_disable(sdma->clk_ipg);
1975 clk_disable(sdma->clk_ahb);
1977 sdma_add_scripts(sdma, addr);
1979 sdma->fw_loaded = true;
1981 dev_info(sdma->dev, "loaded firmware %d.%d\n",
1991 static int sdma_event_remap(struct sdma_engine *sdma)
1993 struct device_node *np = sdma->dev->of_node;
1997 char propname[] = "fsl,sdma-event-remap";
2007 dev_dbg(sdma->dev, "no event needs to be remapped\n");
2010 dev_err(sdma->dev, "the property %s must modulo %d\n",
2018 dev_err(sdma->dev, "failed to get gpr regmap\n");
2026 dev_err(sdma->dev, "failed to read property %s index %d\n",
2033 dev_err(sdma->dev, "failed to read property %s index %d\n",
2040 dev_err(sdma->dev, "failed to read property %s index %d\n",
2055 static int sdma_get_firmware(struct sdma_engine *sdma,
2061 FW_ACTION_UEVENT, fw_name, sdma->dev,
2062 GFP_KERNEL, sdma, sdma_load_firmware);
2067 static int sdma_init(struct sdma_engine *sdma)
2072 ret = clk_enable(sdma->clk_ipg);
2075 ret = clk_enable(sdma->clk_ahb);
2079 if (sdma->drvdata->check_ratio &&
2080 (clk_get_rate(sdma->clk_ahb) == clk_get_rate(sdma->clk_ipg)))
2081 sdma->clk_ratio = 1;
2084 writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
2086 sdma->channel_control = dma_alloc_coherent(sdma->dev,
2091 if (!sdma->channel_control) {
2096 sdma->context = (void *)sdma->channel_control +
2098 sdma->context_phys = ccb_phys +
2102 for (i = 0; i < sdma->drvdata->num_events; i++)
2103 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i));
2107 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
2109 ret = sdma_request_channel0(sdma);
2113 sdma_config_ownership(&sdma->channel[0], false, true, false);
2116 writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
2119 if (sdma->clk_ratio)
2120 writel_relaxed(SDMA_H_CONFIG_ACR, sdma->regs + SDMA_H_CONFIG);
2122 writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
2124 writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
2127 sdma_set_channel_priority(&sdma->channel[0], 7);
2129 clk_disable(sdma->clk_ipg);
2130 clk_disable(sdma->clk_ahb);
2135 clk_disable(sdma->clk_ahb);
2137 clk_disable(sdma->clk_ipg);
2138 dev_err(sdma->dev, "initialisation failed with %d\n", ret);
2159 struct sdma_engine *sdma = ofdma->of_dma_data;
2160 dma_cap_mask_t mask = sdma->dma_device.cap_mask;
2191 struct sdma_engine *sdma;
2198 sdma = devm_kzalloc(&pdev->dev, sizeof(*sdma), GFP_KERNEL);
2199 if (!sdma)
2202 spin_lock_init(&sdma->channel_0_lock);
2204 sdma->dev = &pdev->dev;
2205 sdma->drvdata = of_device_get_match_data(sdma->dev);
2211 sdma->regs = devm_platform_ioremap_resource(pdev, 0);
2212 if (IS_ERR(sdma->regs))
2213 return PTR_ERR(sdma->regs);
2215 sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2216 if (IS_ERR(sdma->clk_ipg))
2217 return PTR_ERR(sdma->clk_ipg);
2219 sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
2220 if (IS_ERR(sdma->clk_ahb))
2221 return PTR_ERR(sdma->clk_ahb);
2223 ret = clk_prepare(sdma->clk_ipg);
2227 ret = clk_prepare(sdma->clk_ahb);
2232 dev_name(&pdev->dev), sdma);
2236 sdma->irq = irq;
2238 sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
2239 if (!sdma->script_addrs) {
2245 saddr_arr = (s32 *)sdma->script_addrs;
2246 for (i = 0; i < sizeof(*sdma->script_addrs) / sizeof(s32); i++)
2249 dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
2250 dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
2251 dma_cap_set(DMA_MEMCPY, sdma->dma_device.cap_mask);
2252 dma_cap_set(DMA_PRIVATE, sdma->dma_device.cap_mask);
2254 INIT_LIST_HEAD(&sdma->dma_device.channels);
2257 struct sdma_channel *sdmac = &sdma->channel[i];
2259 sdmac->sdma = sdma;
2269 * that channel 0 in dmaengine counting matches sdma channel 1.
2272 vchan_init(&sdmac->vc, &sdma->dma_device);
2275 ret = sdma_init(sdma);
2279 ret = sdma_event_remap(sdma);
2283 if (sdma->drvdata->script_addrs)
2284 sdma_add_scripts(sdma, sdma->drvdata->script_addrs);
2286 sdma->dma_device.dev = &pdev->dev;
2288 sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
2289 sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
2290 sdma->dma_device.device_tx_status = sdma_tx_status;
2291 sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
2292 sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
2293 sdma->dma_device.device_config = sdma_config;
2294 sdma->dma_device.device_terminate_all = sdma_terminate_all;
2295 sdma->dma_device.device_synchronize = sdma_channel_synchronize;
2296 sdma->dma_device.src_addr_widths = SDMA_DMA_BUSWIDTHS;
2297 sdma->dma_device.dst_addr_widths = SDMA_DMA_BUSWIDTHS;
2298 sdma->dma_device.directions = SDMA_DMA_DIRECTIONS;
2299 sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
2300 sdma->dma_device.device_prep_dma_memcpy = sdma_prep_memcpy;
2301 sdma->dma_device.device_issue_pending = sdma_issue_pending;
2302 sdma->dma_device.copy_align = 2;
2303 dma_set_max_seg_size(sdma->dma_device.dev, SDMA_BD_MAX_CNT);
2305 platform_set_drvdata(pdev, sdma);
2307 ret = dma_async_device_register(&sdma->dma_device);
2314 ret = of_dma_controller_register(np, sdma_xlate, sdma);
2323 sdma->spba_start_addr = spba_res.start;
2324 sdma->spba_end_addr = spba_res.end;
2334 ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
2339 ret = sdma_get_firmware(sdma, fw_name);
2347 dma_async_device_unregister(&sdma->dma_device);
2349 kfree(sdma->script_addrs);
2351 clk_unprepare(sdma->clk_ahb);
2353 clk_unprepare(sdma->clk_ipg);
2359 struct sdma_engine *sdma = platform_get_drvdata(pdev);
2362 devm_free_irq(&pdev->dev, sdma->irq, sdma);
2363 dma_async_device_unregister(&sdma->dma_device);
2364 kfree(sdma->script_addrs);
2365 clk_unprepare(sdma->clk_ahb);
2366 clk_unprepare(sdma->clk_ipg);
2369 struct sdma_channel *sdmac = &sdma->channel[i];
2380 .name = "imx-sdma",
2392 MODULE_FIRMWARE("imx/sdma/sdma-imx6q.bin");
2395 MODULE_FIRMWARE("imx/sdma/sdma-imx7d.bin");