Lines Matching refs:dma_dev
188 * @dma_dev: holds the dmaengine device
204 struct dma_device dma_dev;
1322 struct dma_device *dma_dev;
1329 dma_dev = &edma->dma_dev;
1333 INIT_LIST_HEAD(&dma_dev->channels);
1338 edmac->chan.device = dma_dev;
1357 &dma_dev->channels);
1360 dma_cap_zero(dma_dev->cap_mask);
1361 dma_cap_set(DMA_SLAVE, dma_dev->cap_mask);
1362 dma_cap_set(DMA_CYCLIC, dma_dev->cap_mask);
1364 dma_dev->dev = &pdev->dev;
1365 dma_dev->device_alloc_chan_resources = ep93xx_dma_alloc_chan_resources;
1366 dma_dev->device_free_chan_resources = ep93xx_dma_free_chan_resources;
1367 dma_dev->device_prep_slave_sg = ep93xx_dma_prep_slave_sg;
1368 dma_dev->device_prep_dma_cyclic = ep93xx_dma_prep_dma_cyclic;
1369 dma_dev->device_config = ep93xx_dma_slave_config;
1370 dma_dev->device_synchronize = ep93xx_dma_synchronize;
1371 dma_dev->device_terminate_all = ep93xx_dma_terminate_all;
1372 dma_dev->device_issue_pending = ep93xx_dma_issue_pending;
1373 dma_dev->device_tx_status = ep93xx_dma_tx_status;
1375 dma_set_max_seg_size(dma_dev->dev, DMA_MAX_CHAN_BYTES);
1378 dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
1379 dma_dev->device_prep_dma_memcpy = ep93xx_dma_prep_dma_memcpy;
1386 dma_cap_set(DMA_PRIVATE, dma_dev->cap_mask);
1395 ret = dma_async_device_register(dma_dev);
1404 dev_info(dma_dev->dev, "EP93xx M2%s DMA ready\n",