drivers/dma/ep93xx_dma.c

232  * @desc: head of the new active descriptor chain
234  * Sets @desc to be the head of the new active descriptor chain. This is the
241 				  struct ep93xx_dma_desc *desc)
245 	list_add_tail(&desc->node, &edmac->active);
247 	/* Flatten the @desc->tx_list chain into @edmac->active list */
248 	while (!list_empty(&desc->tx_list)) {
249 		struct ep93xx_dma_desc *d = list_first_entry(&desc->tx_list,
258 		d->txd.callback = desc->txd.callback;
259 		d->txd.callback_param = desc->txd.callback_param;
287 	struct ep93xx_dma_desc *desc;
294 	desc = ep93xx_dma_get_active(edmac);
295 	if (!desc)
302 	return !desc->txd.cookie;
365 	struct ep93xx_dma_desc *desc;
368 	desc = ep93xx_dma_get_active(edmac);
369 	if (!desc) {
375 		bus_addr = desc->src_addr;
377 		bus_addr = desc->dst_addr;
380 		writel(desc->size, edmac->regs + M2P_MAXCNT0);
383 		writel(desc->size, edmac->regs + M2P_MAXCNT1);
411 		struct ep93xx_dma_desc *desc = ep93xx_dma_get_active(edmac);
430 			desc->txd.cookie, desc->src_addr, desc->dst_addr,
431 			desc->size);
528 	struct ep93xx_dma_desc *desc;
530 	desc = ep93xx_dma_get_active(edmac);
531 	if (!desc) {
537 		writel(desc->src_addr, edmac->regs + M2M_SAR_BASE0);
538 		writel(desc->dst_addr, edmac->regs + M2M_DAR_BASE0);
539 		writel(desc->size, edmac->regs + M2M_BCR0);
541 		writel(desc->src_addr, edmac->regs + M2M_SAR_BASE1);
542 		writel(desc->dst_addr, edmac->regs + M2M_DAR_BASE1);
543 		writel(desc->size, edmac->regs + M2M_BCR1);
605 	struct ep93xx_dma_desc *desc;
620 	desc = ep93xx_dma_get_active(edmac);
621 	last_done = !desc || desc->txd.cookie;
679 	struct ep93xx_dma_desc *desc, *_desc;
684 	list_for_each_entry_safe(desc, _desc, &edmac->free_list, node) {
685 		if (async_tx_test_ack(&desc->txd)) {
686 			list_del_init(&desc->node);
689 			desc->src_addr = 0;
690 			desc->dst_addr = 0;
691 			desc->size = 0;
692 			desc->complete = false;
693 			desc->txd.cookie = 0;
694 			desc->txd.callback = NULL;
695 			desc->txd.callback_param = NULL;
697 			ret = desc;
706 				struct ep93xx_dma_desc *desc)
708 	if (desc) {
712 		list_splice_init(&desc->tx_list, &edmac->free_list);
713 		list_add(&desc->node, &edmac->free_list);
751 	struct ep93xx_dma_desc *desc, *d;
762 	desc = ep93xx_dma_get_active(edmac);
763 	if (desc) {
764 		if (desc->complete) {
767 				dma_cookie_complete(&desc->txd);
770 		dmaengine_desc_get_callback(&desc->txd, &cb);
778 	list_for_each_entry_safe(desc, d, &list, node) {
779 		dma_descriptor_unmap(&desc->txd);
780 		ep93xx_dma_desc_put(edmac, desc);
789 	struct ep93xx_dma_desc *desc;
794 	desc = ep93xx_dma_get_active(edmac);
795 	if (!desc) {
804 		desc->complete = true;
834 	struct ep93xx_dma_desc *desc;
841 	desc = container_of(tx, struct ep93xx_dma_desc, txd);
849 		ep93xx_dma_set_active(edmac, desc);
852 		list_add_tail(&desc->node, &edmac->queue);
917 		struct ep93xx_dma_desc *desc;
919 		desc = kzalloc(sizeof(*desc), GFP_KERNEL);
920 		if (!desc) {
925 		INIT_LIST_HEAD(&desc->tx_list);
927 		dma_async_tx_descriptor_init(&desc->txd, chan);
928 		desc->txd.flags = DMA_CTRL_ACK;
929 		desc->txd.tx_submit = ep93xx_dma_tx_submit;
931 		ep93xx_dma_desc_put(edmac, desc);
954 	struct ep93xx_dma_desc *desc, *d;
969 	list_for_each_entry_safe(desc, d, &list, node)
970 		kfree(desc);
991 	struct ep93xx_dma_desc *desc, *first;
996 		desc = ep93xx_dma_desc_get(edmac);
997 		if (!desc) {
1004 		desc->src_addr = src + offset;
1005 		desc->dst_addr = dest + offset;
1006 		desc->size = bytes;
1009 			first = desc;
1011 			list_add_tail(&desc->node, &first->tx_list);
1040 	struct ep93xx_dma_desc *desc, *first;
1068 		desc = ep93xx_dma_desc_get(edmac);
1069 		if (!desc) {
1075 			desc->src_addr = sg_dma_address(sg);
1076 			desc->dst_addr = edmac->runtime_addr;
1078 			desc->src_addr = edmac->runtime_addr;
1079 			desc->dst_addr = sg_dma_address(sg);
1081 		desc->size = len;
1084 			first = desc;
1086 			list_add_tail(&desc->node, &first->tx_list);
1122 	struct ep93xx_dma_desc *desc, *first;
1148 		desc = ep93xx_dma_desc_get(edmac);
1149 		if (!desc) {
1155 			desc->src_addr = dma_addr + offset;
1156 			desc->dst_addr = edmac->runtime_addr;
1158 			desc->src_addr = edmac->runtime_addr;
1159 			desc->dst_addr = dma_addr + offset;
1162 		desc->size = period_len;
1165 			first = desc;
1167 			list_add_tail(&desc->node, &first->tx_list);
1209 	struct ep93xx_dma_desc *desc, *_d;
1226 	list_for_each_entry_safe(desc, _d, &list, node)
1227 		ep93xx_dma_desc_put(edmac, desc);