Lines Matching refs:dw
79 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
83 desc = dma_pool_zalloc(dw->desc_pool, GFP_ATOMIC, &phys);
98 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
106 dma_pool_free(dw->desc_pool, child, child->txd.phys);
110 dma_pool_free(dw->desc_pool, desc, desc->txd.phys);
116 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
118 dw->initialize_chan(dwc);
121 channel_set_bit(dw, MASK.XFER, dwc->mask);
122 channel_set_bit(dw, MASK.ERROR, dwc->mask);
138 static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc)
140 channel_clear_bit(dw, CH_EN, dwc->mask);
141 while (dma_readl(dw, CH_EN) & dwc->mask)
151 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
164 channel_set_bit(dw, CH_EN, dwc->mask);
173 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
178 if (dma_readl(dw, CH_EN) & dwc->mask) {
213 channel_set_bit(dw, CH_EN, dwc->mask);
259 static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc)
266 if (dma_readl(dw, CH_EN) & dwc->mask) {
271 dwc_chan_disable(dw, dwc);
290 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
294 return dw->block2bytes(dwc, ctlhi, ctllo >> 4 & 7);
297 static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
307 status_xfer = dma_readl(dw, RAW.XFER);
311 dma_writel(dw, CLEAR.XFER, dwc->mask);
345 dwc_complete_all(dw, dwc);
404 dwc_chan_disable(dw, dwc);
420 static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
426 dwc_scan_descriptors(dw, dwc);
440 dma_writel(dw, CLEAR.ERROR, dwc->mask);
465 struct dw_dma *dw = from_tasklet(dw, t, tasklet);
471 status_xfer = dma_readl(dw, RAW.XFER);
472 status_err = dma_readl(dw, RAW.ERROR);
474 dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err);
476 for (i = 0; i < dw->dma.chancnt; i++) {
477 dwc = &dw->chan[i];
479 dev_vdbg(dw->dma.dev, "Cyclic xfer is not implemented\n");
481 dwc_handle_error(dw, dwc);
483 dwc_scan_descriptors(dw, dwc);
487 channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
488 channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
493 struct dw_dma *dw = dev_id;
497 if (!dw->in_use)
500 status = dma_readl(dw, STATUS_INT);
501 dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status);
511 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
512 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
513 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
515 status = dma_readl(dw, STATUS_INT);
517 dev_err(dw->dma.dev,
522 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
523 channel_clear_bit(dw, MASK.BLOCK, (1 << 8) - 1);
524 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
525 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
526 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
529 tasklet_schedule(&dw->tasklet);
541 struct dw_dma *dw = to_dw_dma(chan->device);
550 unsigned int data_width = dw->pdata->data_width[m_master];
567 ctllo = dw->prepare_ctllo(dwc)
580 ctlhi = dw->bytes2block(dwc, len - offset, src_width, &xfer_count);
619 struct dw_dma *dw = to_dw_dma(chan->device);
629 unsigned int data_width = dw->pdata->data_width[m_master];
647 ctllo = dw->prepare_ctllo(dwc)
670 ctlhi = dw->bytes2block(dwc, len, mem_width, &dlen);
697 ctllo = dw->prepare_ctllo(dwc)
718 ctlhi = dw->bytes2block(dwc, len, reg_width, &dlen);
786 struct dw_dma *dw = to_dw_dma(chan->device);
795 dw->encode_maxburst(dwc, &dwc->dma_sconfig.src_maxburst);
796 dw->encode_maxburst(dwc, &dwc->dma_sconfig.dst_maxburst);
803 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
806 dw->suspend_chan(dwc, drain);
828 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
830 dw->resume_chan(dwc, drain);
853 struct dw_dma *dw = to_dw_dma(chan->device);
864 dwc_chan_disable(dw, dwc);
955 void do_dw_dma_off(struct dw_dma *dw)
957 dma_writel(dw, CFG, 0);
959 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
960 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
961 channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
962 channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
963 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
965 while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
969 void do_dw_dma_on(struct dw_dma *dw)
971 dma_writel(dw, CFG, DW_CFG_DMA_EN);
977 struct dw_dma *dw = to_dw_dma(chan->device);
982 if (dma_readl(dw, CH_EN) & dwc->mask) {
1004 if (!dw->in_use)
1005 do_dw_dma_on(dw);
1006 dw->in_use |= dwc->mask;
1014 struct dw_dma *dw = to_dw_dma(chan->device);
1031 channel_clear_bit(dw, MASK.XFER, dwc->mask);
1032 channel_clear_bit(dw, MASK.BLOCK, dwc->mask);
1033 channel_clear_bit(dw, MASK.ERROR, dwc->mask);
1038 dw->in_use &= ~dwc->mask;
1039 if (!dw->in_use)
1040 do_dw_dma_off(dw);
1066 struct dw_dma *dw = chip->dw;
1073 dw->pdata = devm_kzalloc(chip->dev, sizeof(*dw->pdata), GFP_KERNEL);
1074 if (!dw->pdata)
1077 dw->regs = chip->regs;
1082 dw_params = dma_readl(dw, DW_PARAMS);
1092 pdata = dw->pdata;
1101 pdata->block_size = dma_readl(dw, MAX_BLK_SIZE);
1110 memcpy(dw->pdata, chip->pdata, sizeof(*dw->pdata));
1113 pdata = dw->pdata;
1116 dw->chan = devm_kcalloc(chip->dev, pdata->nr_channels, sizeof(*dw->chan),
1118 if (!dw->chan) {
1124 dw->all_chan_mask = (1 << pdata->nr_channels) - 1;
1127 dw->disable(dw);
1130 dw->set_device_name(dw, chip->id);
1133 dw->desc_pool = dmam_pool_create(dw->name, chip->dev,
1135 if (!dw->desc_pool) {
1141 tasklet_setup(&dw->tasklet, dw_dma_tasklet);
1144 dw->name, dw);
1148 INIT_LIST_HEAD(&dw->dma.channels);
1150 struct dw_dma_chan *dwc = &dw->chan[i];
1152 dwc->chan.device = &dw->dma;
1156 &dw->dma.channels);
1158 list_add(&dwc->chan.device_node, &dw->dma.channels);
1166 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
1173 channel_clear_bit(dw, CH_EN, dwc->mask);
1180 void __iomem *addr = &__dw_regs(dw)->DWC_PARAMS[r];
1214 dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
1215 dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
1216 dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
1217 dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
1218 dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
1221 dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1222 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
1223 dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1225 dw->dma.dev = chip->dev;
1226 dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
1227 dw->dma.device_free_chan_resources = dwc_free_chan_resources;
1229 dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
1230 dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
1232 dw->dma.device_caps = dwc_caps;
1233 dw->dma.device_config = dwc_config;
1234 dw->dma.device_pause = dwc_pause;
1235 dw->dma.device_resume = dwc_resume;
1236 dw->dma.device_terminate_all = dwc_terminate_all;
1238 dw->dma.device_tx_status = dwc_tx_status;
1239 dw->dma.device_issue_pending = dwc_issue_pending;
1242 dw->dma.min_burst = DW_DMA_MIN_BURST;
1243 dw->dma.max_burst = DW_DMA_MAX_BURST;
1244 dw->dma.src_addr_widths = DW_DMA_BUSWIDTHS;
1245 dw->dma.dst_addr_widths = DW_DMA_BUSWIDTHS;
1246 dw->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) |
1248 dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1255 dma_set_max_seg_size(dw->dma.dev, dw->chan[0].block_size);
1257 err = dma_async_device_register(&dw->dma);
1269 free_irq(chip->irq, dw);
1277 struct dw_dma *dw = chip->dw;
1282 do_dw_dma_off(dw);
1283 dma_async_device_unregister(&dw->dma);
1285 free_irq(chip->irq, dw);
1286 tasklet_kill(&dw->tasklet);
1288 list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
1291 channel_clear_bit(dw, CH_EN, dwc->mask);
1300 struct dw_dma *dw = chip->dw;
1302 dw->disable(dw);
1309 struct dw_dma *dw = chip->dw;
1311 dw->enable(dw);