dma/dw-edma/dw-edma-v0-core.c

13 #include "dw-edma-core.h"
14 #include "dw-edma-v0-core.h"
15 #include "dw-edma-v0-regs.h"
16 #include "dw-edma-v0-debugfs.h"
28 static inline struct dw_edma_v0_regs __iomem *__dw_regs(struct dw_edma *dw)
30 	return dw->chip->reg_base;
33 #define SET_32(dw, name, value)				\
34 	writel(value, &(__dw_regs(dw)->name))
36 #define GET_32(dw, name)				\
37 	readl(&(__dw_regs(dw)->name))
39 #define SET_RW_32(dw, dir, name, value)			\
42 			SET_32(dw, wr_##name, value);	\
44 			SET_32(dw, rd_##name, value);	\
47 #define GET_RW_32(dw, dir, name)			\
49 	  ? GET_32(dw, wr_##name)			\
50 	  : GET_32(dw, rd_##name))
52 #define SET_BOTH_32(dw, name, value)			\
54 		SET_32(dw, wr_##name, value);		\
55 		SET_32(dw, rd_##name, value);		\
58 #define SET_64(dw, name, value)				\
59 	writeq(value, &(__dw_regs(dw)->name))
61 #define GET_64(dw, name)				\
62 	readq(&(__dw_regs(dw)->name))
64 #define SET_RW_64(dw, dir, name, value)			\
67 			SET_64(dw, wr_##name, value);	\
69 			SET_64(dw, rd_##name, value);	\
72 #define GET_RW_64(dw, dir, name)			\
74 	  ? GET_64(dw, wr_##name)			\
75 	  : GET_64(dw, rd_##name))
77 #define SET_BOTH_64(dw, name, value)			\
79 		SET_64(dw, wr_##name, value);		\
80 		SET_64(dw, rd_##name, value);		\
83 #define SET_COMPAT(dw, name, value)			\
84 	writel(value, &(__dw_regs(dw)->type.unroll.name))
86 #define SET_RW_COMPAT(dw, dir, name, value)		\
89 			SET_COMPAT(dw, wr_##name, value); \
91 			SET_COMPAT(dw, rd_##name, value); \
95 __dw_ch_regs(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch)
97 	if (dw->chip->mf == EDMA_MF_EDMA_LEGACY)
98 		return &(__dw_regs(dw)->type.legacy.ch);
101 		return &__dw_regs(dw)->type.unroll.ch[ch].wr;
103 	return &__dw_regs(dw)->type.unroll.ch[ch].rd;
106 static inline void writel_ch(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch,
109 	if (dw->chip->mf == EDMA_MF_EDMA_LEGACY) {
113 		raw_spin_lock_irqsave(&dw->lock, flags);
120 		       &(__dw_regs(dw)->type.legacy.viewport_sel));
123 		raw_spin_unlock_irqrestore(&dw->lock, flags);
129 static inline u32 readl_ch(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch,
134 	if (dw->chip->mf == EDMA_MF_EDMA_LEGACY) {
138 		raw_spin_lock_irqsave(&dw->lock, flags);
145 		       &(__dw_regs(dw)->type.legacy.viewport_sel));
148 		raw_spin_unlock_irqrestore(&dw->lock, flags);
156 #define SET_CH_32(dw, dir, ch, name, value) \
157 	writel_ch(dw, dir, ch, value, &(__dw_ch_regs(dw, dir, ch)->name))
159 #define GET_CH_32(dw, dir, ch, name) \
160 	readl_ch(dw, dir, ch, &(__dw_ch_regs(dw, dir, ch)->name))
163 static void dw_edma_v0_core_off(struct dw_edma *dw)
165 	SET_BOTH_32(dw, int_mask,
167 	SET_BOTH_32(dw, int_clear,
169 	SET_BOTH_32(dw, engine_en, 0);
172 static u16 dw_edma_v0_core_ch_count(struct dw_edma *dw, enum dw_edma_dir dir)
178 				   GET_32(dw, ctrl));
181 				   GET_32(dw, ctrl));
191 	struct dw_edma *dw = chan->dw;
195 			GET_CH_32(dw, chan->dir, chan->id, ch_control1));
207 	struct dw_edma *dw = chan->dw;
209 	SET_RW_32(dw, chan->dir, int_clear,
215 	struct dw_edma *dw = chan->dw;
217 	SET_RW_32(dw, chan->dir, int_clear,
221 static u32 dw_edma_v0_core_status_done_int(struct dw_edma *dw, enum dw_edma_dir dir)
224 			 GET_RW_32(dw, dir, int_status));
227 static u32 dw_edma_v0_core_status_abort_int(struct dw_edma *dw, enum dw_edma_dir dir)
230 			 GET_RW_32(dw, dir, int_status));
237 	struct dw_edma *dw = dw_irq->dw;
245 		total = dw->wr_ch_cnt;
249 		total = dw->rd_ch_cnt;
250 		off = dw->wr_ch_cnt;
254 	val = dw_edma_v0_core_status_done_int(dw, dir);
257 		chan = &dw->chan[pos + off];
265 	val = dw_edma_v0_core_status_abort_int(dw, dir);
268 		chan = &dw->chan[pos + off];
284 	if (chunk->chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL) {
306 	if (chunk->chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL) {
334 			if (!(chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL))
359 	if (!(chunk->chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL))
366 	struct dw_edma *dw = chan->dw;
373 		SET_RW_32(dw, chan->dir, engine_en, BIT(0));
374 		if (dw->chip->mf == EDMA_MF_HDMA_COMPAT) {
377 				SET_RW_COMPAT(dw, chan->dir, ch0_pwr_en,
381 				SET_RW_COMPAT(dw, chan->dir, ch1_pwr_en,
385 				SET_RW_COMPAT(dw, chan->dir, ch2_pwr_en,
389 				SET_RW_COMPAT(dw, chan->dir, ch3_pwr_en,
393 				SET_RW_COMPAT(dw, chan->dir, ch4_pwr_en,
397 				SET_RW_COMPAT(dw, chan->dir, ch5_pwr_en,
401 				SET_RW_COMPAT(dw, chan->dir, ch6_pwr_en,
405 				SET_RW_COMPAT(dw, chan->dir, ch7_pwr_en,
411 		tmp = GET_RW_32(dw, chan->dir, int_mask);
414 		SET_RW_32(dw, chan->dir, int_mask, tmp);
416 		tmp = GET_RW_32(dw, chan->dir, linked_list_err_en);
418 		SET_RW_32(dw, chan->dir, linked_list_err_en, tmp);
420 		SET_CH_32(dw, chan->dir, chan->id, ch_control1,
424 		SET_CH_32(dw, chan->dir, chan->id, llp.lsb,
426 		SET_CH_32(dw, chan->dir, chan->id, llp.msb,
433 	SET_RW_32(dw, chan->dir, doorbell,
439 	struct dw_edma *dw = chan->dw;
443 	SET_RW_32(dw, chan->dir, done_imwr.lsb, chan->msi.address_lo);
444 	SET_RW_32(dw, chan->dir, done_imwr.msb, chan->msi.address_hi);
446 	SET_RW_32(dw, chan->dir, abort_imwr.lsb, chan->msi.address_lo);
447 	SET_RW_32(dw, chan->dir, abort_imwr.msb, chan->msi.address_hi);
452 		tmp = GET_RW_32(dw, chan->dir, ch01_imwr_data);
457 		tmp = GET_RW_32(dw, chan->dir, ch23_imwr_data);
462 		tmp = GET_RW_32(dw, chan->dir, ch45_imwr_data);
467 		tmp = GET_RW_32(dw, chan->dir, ch67_imwr_data);
486 		SET_RW_32(dw, chan->dir, ch01_imwr_data, tmp);
491 		SET_RW_32(dw, chan->dir, ch23_imwr_data, tmp);
496 		SET_RW_32(dw, chan->dir, ch45_imwr_data, tmp);
501 		SET_RW_32(dw, chan->dir, ch67_imwr_data, tmp);
507 static void dw_edma_v0_core_debugfs_on(struct dw_edma *dw)
509 	dw_edma_v0_debugfs_on(dw);
522 void dw_edma_v0_core_register(struct dw_edma *dw)
524 	dw->core = &dw_edma_v0_core;