dma/dw-axi-dmac/dw-axi-dmac-platform.c

105 	if (chan->chip->dw->hdata->reg_map_8_channels &&
106 	    !chan->chip->dw->hdata->use_cfg2) {
198 	if (chan->chip->dw->hdata->nr_channels >= DMAC_CHAN_16) {
213 		if (chan->chip->dw->hdata->reg_map_8_channels)
225 	if (chan->chip->dw->hdata->nr_channels >= DMAC_CHAN_16) {
239 		if (chan->chip->dw->hdata->reg_map_8_channels) {
254 	if (chan->chip->dw->hdata->nr_channels >= DMAC_CHAN_16)
270 	for (i = 0; i < chip->dw->hdata->nr_channels; i++) {
282 	u32 max_width = chan->chip->dw->hdata->m_data_width;
425 	u32 priority = chan->chip->dw->hdata->priority[chan->id];
640 	if (desc->chan->chip->dw->hdata->nr_masters > 1)
652 	unsigned int data_width = BIT(chan->chip->dw->hdata->m_data_width);
661 	axi_block_ts = chan->chip->dw->hdata->block_size[chan->id];
704 	if (chan->chip->dw->hdata->restrict_axi_burst_len) {
705 		burst_len = chan->chip->dw->hdata->axi_rw_burst_len;
740 	axi_block_ts = chan->chip->dw->hdata->block_size[chan->id];
744 		data_width = BIT(chan->chip->dw->hdata->m_data_width);
934 	max_block_ts = chan->chip->dw->hdata->block_size[chan->id];
975 		if (chan->chip->dw->hdata->restrict_axi_burst_len) {
976 			u32 burst_len = chan->chip->dw->hdata->axi_rw_burst_len;
1163 	for (i = 0; i < dw->hdata->nr_channels; i++) {
1228 	if (chan->chip->dw->hdata->nr_channels >= DMAC_CHAN_16) {
1241 		if (chan->chip->dw->hdata->reg_map_8_channels) {
1275 	if (chan->chip->dw->hdata->nr_channels >= DMAC_CHAN_16) {
1288 		if (chan->chip->dw->hdata->reg_map_8_channels) {
1390 	chip->dw->hdata->nr_channels = tmp;
1392 		chip->dw->hdata->reg_map_8_channels = true;
1400 	chip->dw->hdata->nr_masters = tmp;
1408 	chip->dw->hdata->m_data_width = tmp;
1411 					     chip->dw->hdata->nr_channels);
1414 	for (tmp = 0; tmp < chip->dw->hdata->nr_channels; tmp++) {
1418 		chip->dw->hdata->block_size[tmp] = carr[tmp];
1422 					     chip->dw->hdata->nr_channels);
1426 	for (tmp = 0; tmp < chip->dw->hdata->nr_channels; tmp++) {
1427 		if (carr[tmp] >= chip->dw->hdata->nr_channels)
1430 		chip->dw->hdata->priority[tmp] = carr[tmp];
1441 		chip->dw->hdata->restrict_axi_burst_len = true;
1442 		chip->dw->hdata->axi_rw_burst_len = tmp;
1452 	struct dw_axi_dma_hcfg *hdata;
1466 	hdata = devm_kzalloc(&pdev->dev, sizeof(*hdata), GFP_KERNEL);
1467 	if (!hdata)
1472 	chip->dw->hdata = hdata;
1499 	chip->dw->hdata->use_cfg2 = !!(flags & AXI_DMA_FLAG_USE_CFG2);
1513 	dw->chan = devm_kcalloc(chip->dev, hdata->nr_channels,
1524 	for (i = 0; i < hdata->nr_channels; i++) {
1542 	dw->dma.max_burst = hdata->axi_rw_burst_len;
1602 		 dw->hdata->nr_channels);
1623 	for (i = 0; i < dw->hdata->nr_channels; i++) {