drivers/dma/dma-axi-dmac.c

170 	struct dma_device dma_dev;
177 		dma_dev);
357 			dev_dbg(dmac->dma_dev.dev,
361 			dev_warn(dmac->dma_dev.dev,
534 	struct device *dev = dmac->dma_dev.dev;
573 	struct device *dev = dmac->dma_dev.dev;
978 		dev_err(dmac->dma_dev.dev,
986 		dev_err(dmac->dma_dev.dev,
1007 	struct dma_device *dma_dev;
1050 	dma_dev = &dmac->dma_dev;
1051 	dma_cap_set(DMA_SLAVE, dma_dev->cap_mask);
1052 	dma_cap_set(DMA_CYCLIC, dma_dev->cap_mask);
1053 	dma_cap_set(DMA_INTERLEAVE, dma_dev->cap_mask);
1054 	dma_dev->device_free_chan_resources = axi_dmac_free_chan_resources;
1055 	dma_dev->device_tx_status = dma_cookie_status;
1056 	dma_dev->device_issue_pending = axi_dmac_issue_pending;
1057 	dma_dev->device_prep_slave_sg = axi_dmac_prep_slave_sg;
1058 	dma_dev->device_prep_dma_cyclic = axi_dmac_prep_dma_cyclic;
1059 	dma_dev->device_prep_interleaved_dma = axi_dmac_prep_interleaved;
1060 	dma_dev->device_terminate_all = axi_dmac_terminate_all;
1061 	dma_dev->device_synchronize = axi_dmac_synchronize;
1062 	dma_dev->dev = &pdev->dev;
1063 	dma_dev->src_addr_widths = BIT(dmac->chan.src_width);
1064 	dma_dev->dst_addr_widths = BIT(dmac->chan.dest_width);
1065 	dma_dev->directions = BIT(dmac->chan.direction);
1066 	dma_dev->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
1067 	dma_dev->max_sg_burst = 31; /* 31 SGs maximum in one burst */
1068 	INIT_LIST_HEAD(&dma_dev->channels);
1071 	vchan_init(&dmac->chan.vchan, dma_dev);
1077 	dma_dev->copy_align = (dmac->chan.address_align_mask + 1);
1089 			dev_err(dmac->dma_dev.dev,
1096 	ret = dma_async_device_register(dma_dev);
1101 		of_dma_xlate_by_chan_id, dma_dev);
1126 	dma_async_device_unregister(&dmac->dma_dev);
1140 	dma_async_device_unregister(&dmac->dma_dev);