Lines Matching refs:dmac

27 #include <dt-bindings/dma/axi-dmac.h>
229 struct axi_dmac *dmac = chan_to_axi_dmac(chan);
237 val = axi_dmac_read(dmac, AXI_DMAC_REG_START_TRANSFER);
272 sg->hw->id = axi_dmac_read(dmac, AXI_DMAC_REG_TRANSFER_ID);
276 axi_dmac_write(dmac, AXI_DMAC_REG_DEST_ADDRESS, sg->hw->dest_addr);
277 axi_dmac_write(dmac, AXI_DMAC_REG_DEST_STRIDE, sg->hw->dst_stride);
281 axi_dmac_write(dmac, AXI_DMAC_REG_SRC_ADDRESS, sg->hw->src_addr);
282 axi_dmac_write(dmac, AXI_DMAC_REG_SRC_STRIDE, sg->hw->src_stride);
301 axi_dmac_write(dmac, AXI_DMAC_REG_SG_ADDRESS, (u32)sg->hw_phys);
302 axi_dmac_write(dmac, AXI_DMAC_REG_SG_ADDRESS_HIGH,
305 axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, sg->hw->x_len);
306 axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, sg->hw->y_len);
308 axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, flags);
309 axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 1);
329 struct axi_dmac *dmac = chan_to_axi_dmac(chan);
336 len = axi_dmac_read(dmac, AXI_DMAC_REG_PARTIAL_XFER_LEN);
337 id = axi_dmac_read(dmac, AXI_DMAC_REG_PARTIAL_XFER_ID);
357 dev_dbg(dmac->dma_dev.dev,
361 dev_warn(dmac->dma_dev.dev,
367 xfer_done = axi_dmac_read(dmac, AXI_DMAC_REG_TRANSFER_DONE);
460 struct axi_dmac *dmac = devid;
464 pending = axi_dmac_read(dmac, AXI_DMAC_REG_IRQ_PENDING);
468 axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_PENDING, pending);
470 spin_lock(&dmac->chan.vchan.lock);
475 completed = axi_dmac_read(dmac, AXI_DMAC_REG_TRANSFER_DONE);
476 start_next = axi_dmac_transfer_done(&dmac->chan, completed);
480 axi_dmac_start_transfer(&dmac->chan);
481 spin_unlock(&dmac->chan.vchan.lock);
489 struct axi_dmac *dmac = chan_to_axi_dmac(chan);
494 axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, 0);
515 struct axi_dmac *dmac = chan_to_axi_dmac(chan);
522 axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, ctrl);
533 struct axi_dmac *dmac = chan_to_axi_dmac(chan);
534 struct device *dev = dmac->dma_dev.dev;
572 struct axi_dmac *dmac = chan_to_axi_dmac(desc->chan);
573 struct device *dev = dmac->dma_dev.dev;
887 static int axi_dmac_parse_dt(struct device *dev, struct axi_dmac *dmac)
897 ret = axi_dmac_parse_chan_dt(of_chan, &dmac->chan);
909 static int axi_dmac_read_chan_config(struct device *dev, struct axi_dmac *dmac)
911 struct axi_dmac_chan *chan = &dmac->chan;
914 desc = axi_dmac_read(dmac, AXI_DMAC_REG_INTERFACE_DESC);
954 static int axi_dmac_detect_caps(struct axi_dmac *dmac, unsigned int version)
956 struct axi_dmac_chan *chan = &dmac->chan;
958 axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, AXI_DMAC_FLAG_CYCLIC);
959 if (axi_dmac_read(dmac, AXI_DMAC_REG_FLAGS) == AXI_DMAC_FLAG_CYCLIC)
962 axi_dmac_write(dmac, AXI_DMAC_REG_SG_ADDRESS, 0xffffffff);
963 if (axi_dmac_read(dmac, AXI_DMAC_REG_SG_ADDRESS))
966 axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 1);
967 if (axi_dmac_read(dmac, AXI_DMAC_REG_Y_LENGTH) == 1)
970 axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, 0xffffffff);
971 chan->max_length = axi_dmac_read(dmac, AXI_DMAC_REG_X_LENGTH);
975 axi_dmac_write(dmac, AXI_DMAC_REG_DEST_ADDRESS, 0xffffffff);
976 if (axi_dmac_read(dmac, AXI_DMAC_REG_DEST_ADDRESS) == 0 &&
978 dev_err(dmac->dma_dev.dev,
983 axi_dmac_write(dmac, AXI_DMAC_REG_SRC_ADDRESS, 0xffffffff);
984 if (axi_dmac_read(dmac, AXI_DMAC_REG_SRC_ADDRESS) == 0 &&
986 dev_err(dmac->dma_dev.dev,
995 axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, 0x00);
997 axi_dmac_read(dmac, AXI_DMAC_REG_X_LENGTH);
1018 struct axi_dmac *dmac;
1024 dmac = devm_kzalloc(&pdev->dev, sizeof(*dmac), GFP_KERNEL);
1025 if (!dmac)
1028 dmac->irq = platform_get_irq(pdev, 0);
1029 if (dmac->irq < 0)
1030 return dmac->irq;
1031 if (dmac->irq == 0)
1034 dmac->base = devm_platform_ioremap_resource(pdev, 0);
1035 if (IS_ERR(dmac->base))
1036 return PTR_ERR(dmac->base);
1038 dmac->clk = devm_clk_get_enabled(&pdev->dev, NULL);
1039 if (IS_ERR(dmac->clk))
1040 return PTR_ERR(dmac->clk);
1042 version = axi_dmac_read(dmac, ADI_AXI_REG_VERSION);
1045 ret = axi_dmac_read_chan_config(&pdev->dev, dmac);
1047 ret = axi_dmac_parse_dt(&pdev->dev, dmac);
1052 INIT_LIST_HEAD(&dmac->chan.active_descs);
1056 dma_dev = &dmac->dma_dev;
1069 dma_dev->src_addr_widths = BIT(dmac->chan.src_width);
1070 dma_dev->dst_addr_widths = BIT(dmac->chan.dest_width);
1071 dma_dev->directions = BIT(dmac->chan.direction);
1076 dmac->chan.vchan.desc_free = axi_dmac_desc_free;
1077 vchan_init(&dmac->chan.vchan, dma_dev);
1079 ret = axi_dmac_detect_caps(dmac, version);
1083 dma_dev->copy_align = (dmac->chan.address_align_mask + 1);
1085 if (dmac->chan.hw_sg)
1088 axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_MASK, irq_mask);
1091 ret = axi_dmac_read(dmac, AXI_DMAC_REG_COHERENCY_DESC);
1095 dev_err(dmac->dma_dev.dev,
1110 &dmac->chan.vchan.task);
1124 ret = devm_request_irq(&pdev->dev, dmac->irq, axi_dmac_interrupt_handler,
1125 IRQF_SHARED, dev_name(&pdev->dev), dmac);
1129 regmap = devm_regmap_init_mmio(&pdev->dev, dmac->base,
1136 { .compatible = "adi,axi-dmac-1.00.a" },
1143 .name = "dma-axi-dmac",