drivers/dma/apple-admac.c

150 static int admac_alloc_sram_carveout(struct admac_data *ad,
158 		sram = &ad->txcache;
160 		sram = &ad->rxcache;
162 	mutex_lock(&ad->cache_alloc_lock);
177 	mutex_unlock(&ad->cache_alloc_lock);
182 static void admac_free_sram_carveout(struct admac_data *ad,
191 		sram = &ad->txcache;
193 		sram = &ad->rxcache;
198 	mutex_lock(&ad->cache_alloc_lock);
201 	mutex_unlock(&ad->cache_alloc_lock);
204 static void admac_modify(struct admac_data *ad, int reg, u32 mask, u32 val)
206 	void __iomem *addr = ad->base + reg;
285 static void admac_cyclic_write_one_desc(struct admac_data *ad, int channo,
295 	dev_dbg(ad->dev, "ch%d descriptor: addr=0x%pad len=0x%zx flags=0x%lx\n",
298 	writel_relaxed(lower_32_bits(addr), ad->base + REG_DESC_WRITE(channo));
299 	writel_relaxed(upper_32_bits(addr), ad->base + REG_DESC_WRITE(channo));
300 	writel_relaxed(tx->period_len,      ad->base + REG_DESC_WRITE(channo));
301 	writel_relaxed(FLAG_DESC_NOTIFY,    ad->base + REG_DESC_WRITE(channo));
311 static void admac_cyclic_write_desc(struct admac_data *ad, int channo,
317 		if (readl_relaxed(ad->base + REG_DESC_RING(channo)) & RING_FULL)
319 		admac_cyclic_write_one_desc(ad, channo, tx);
343 static u32 admac_cyclic_read_residue(struct admac_data *ad, int channo,
351 	ring1 =    readl_relaxed(ad->base + REG_REPORT_RING(channo));
352 	residue1 = readl_relaxed(ad->base + REG_RESIDUE(channo));
353 	ring2 =    readl_relaxed(ad->base + REG_REPORT_RING(channo));
354 	residue2 = readl_relaxed(ad->base + REG_RESIDUE(channo));
376 	struct admac_data *ad = adchan->host;
392 		residue = admac_cyclic_read_residue(ad, adchan->no, adtx);
411 	struct admac_data *ad = adchan->host;
415 		       ad->base + REG_CHAN_INTSTATUS(adchan->no, ad->irq_index));
417 		       ad->base + REG_CHAN_INTMASK(adchan->no, ad->irq_index));
421 		writel_relaxed(startbit, ad->base + REG_TX_START);
424 		writel_relaxed(startbit, ad->base + REG_RX_START);
434 	struct admac_data *ad = adchan->host;
439 		writel_relaxed(stopbit, ad->base + REG_TX_STOP);
442 		writel_relaxed(stopbit, ad->base + REG_RX_STOP);
452 	struct admac_data *ad = adchan->host;
455 		       ad->base + REG_CHAN_CTL(adchan->no));
456 	writel_relaxed(0, ad->base + REG_CHAN_CTL(adchan->no));
461 	struct admac_data *ad = adchan->host;
465 	writel_relaxed(0, ad->base + REG_CHAN_CTL(ch));
467 	admac_cyclic_write_one_desc(ad, ch, adchan->current_tx);
469 	admac_cyclic_write_desc(ad, ch, adchan->current_tx);
555 	struct admac_data *ad = adchan->host;
559 	ret = admac_alloc_sram_carveout(ad, admac_chan_direction(adchan->no),
565 		       ad->base + REG_CHAN_SRAM_CARVEOUT(adchan->no));
582 	struct admac_data *ad = (struct admac_data *) ofdma->of_dma_data;
590 	if (index >= ad->nchannels) {
591 		dev_err(ad->dev, "channel index %u out of bounds\n", index);
595 	return dma_get_slave_channel(&ad->channels[index].chan);
598 static int admac_drain_reports(struct admac_data *ad, int channo)
605 		if (readl_relaxed(ad->base + REG_REPORT_RING(channo)) & RING_EMPTY)
608 		countval_lo = readl_relaxed(ad->base + REG_REPORT_READ(channo));
609 		countval_hi = readl_relaxed(ad->base + REG_REPORT_READ(channo));
610 		unk1 =        readl_relaxed(ad->base + REG_REPORT_READ(channo));
611 		flags =       readl_relaxed(ad->base + REG_REPORT_READ(channo));
613 		dev_dbg(ad->dev, "ch%d report: countval=0x%llx unk1=0x%x flags=0x%x\n",
620 static void admac_handle_status_err(struct admac_data *ad, int channo)
624 	if (readl_relaxed(ad->base + REG_DESC_RING(channo)) & RING_ERR) {
625 		writel_relaxed(RING_ERR, ad->base + REG_DESC_RING(channo));
626 		dev_err_ratelimited(ad->dev, "ch%d descriptor ring error\n", channo);
630 	if (readl_relaxed(ad->base + REG_REPORT_RING(channo)) & RING_ERR) {
631 		writel_relaxed(RING_ERR, ad->base + REG_REPORT_RING(channo));
632 		dev_err_ratelimited(ad->dev, "ch%d report ring error\n", channo);
637 		dev_err(ad->dev, "ch%d unknown error, masking errors as cause of IRQs\n", channo);
638 		admac_modify(ad, REG_CHAN_INTMASK(channo, ad->irq_index),
643 static void admac_handle_status_desc_done(struct admac_data *ad, int channo)
645 	struct admac_chan *adchan = &ad->channels[channo];
650 		       ad->base + REG_CHAN_INTSTATUS(channo, ad->irq_index));
653 	nreports = admac_drain_reports(ad, channo);
662 		admac_cyclic_write_desc(ad, channo, tx);
668 static void admac_handle_chan_int(struct admac_data *ad, int no)
670 	u32 cause = readl_relaxed(ad->base + REG_CHAN_INTSTATUS(no, ad->irq_index));
673 		admac_handle_status_err(ad, no);
676 		admac_handle_status_desc_done(ad, no);
681 	struct admac_data *ad = devid;
685 	rx_intstate = readl_relaxed(ad->base + REG_RX_INTSTATE(ad->irq_index));
686 	tx_intstate = readl_relaxed(ad->base + REG_TX_INTSTATE(ad->irq_index));
687 	global_intstate = readl_relaxed(ad->base + REG_GLOBAL_INTSTATE(ad->irq_index));
692 	for (i = 0; i < ad->nchannels; i += 2) {
694 			admac_handle_chan_int(ad, i);
698 	for (i = 1; i < ad->nchannels; i += 2) {
700 			admac_handle_chan_int(ad, i);
705 		dev_warn(ad->dev, "clearing unknown global interrupt flag: %x\n",
707 		writel_relaxed(~(u32) 0, ad->base + REG_GLOBAL_INTSTATE(ad->irq_index));
742 	struct admac_data *ad = adchan->host;
745 	u32 bus_width = readl_relaxed(ad->base + REG_BUS_WIDTH(adchan->no)) &
785 	writel_relaxed(bus_width, ad->base + REG_BUS_WIDTH(adchan->no));
796 		       ad->base + REG_CHAN_FIFOCTL(adchan->no));
804 	struct admac_data *ad;
815 	ad = devm_kzalloc(&pdev->dev, struct_size(ad, channels, nchannels), GFP_KERNEL);
816 	if (!ad)
819 	platform_set_drvdata(pdev, ad);
820 	ad->dev = &pdev->dev;
821 	ad->nchannels = nchannels;
822 	mutex_init(&ad->cache_alloc_lock);
831 			ad->irq_index = i;
838 	ad->irq = irq;
840 	ad->base = devm_platform_ioremap_resource(pdev, 0);
841 	if (IS_ERR(ad->base))
842 		return dev_err_probe(&pdev->dev, PTR_ERR(ad->base),
845 	ad->rstc = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
846 	if (IS_ERR(ad->rstc))
847 		return PTR_ERR(ad->rstc);
849 	dma = &ad->dma;
877 		struct admac_chan *adchan = &ad->channels[i];
879 		adchan->host = ad;
881 		adchan->chan.device = &ad->dma;
890 	err = reset_control_reset(ad->rstc);
895 	err = request_irq(irq, admac_interrupt, 0, dev_name(&pdev->dev), ad);
902 	err = dma_async_device_register(&ad->dma);
908 	err = of_dma_controller_register(pdev->dev.of_node, admac_dma_of_xlate, ad);
910 		dma_async_device_unregister(&ad->dma);
915 	ad->txcache.size = readl_relaxed(ad->base + REG_TX_SRAM_SIZE);
916 	ad->rxcache.size = readl_relaxed(ad->base + REG_RX_SRAM_SIZE);
920 		 readl_relaxed(ad->base + REG_IMPRINT), ad->txcache.size, ad->rxcache.size);
925 	free_irq(ad->irq, ad);
927 	reset_control_rearm(ad->rstc);
933 	struct admac_data *ad = platform_get_drvdata(pdev);
936 	dma_async_device_unregister(&ad->dma);
937 	free_irq(ad->irq, ad);
938 	reset_control_rearm(ad->rstc);