Lines Matching refs:rc

203 	int rc;
264 rc = cxl_pci_mbox_wait_for_doorbell(cxlds);
265 if (rc == -ETIMEDOUT) {
269 return rc;
376 int rc;
379 rc = __cxl_pci_mbox_send_cmd(mds, cmd);
382 return rc;
506 int rc;
508 rc = cxl_find_regblock(pdev, type, map);
515 if (rc && type == CXL_REGLOC_RBI_COMPONENT && is_cxl_restricted(pdev))
516 rc = cxl_rcrb_get_comp_regs(pdev, map);
518 if (rc)
519 return rc;
530 int rc;
541 rc = pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap);
542 if (rc)
543 return rc;
661 int rc;
663 rc = cxl_internal_send_cmd(mds, &mbox_cmd);
664 if (rc < 0)
666 "Failed to get event interrupt policy : %d", rc);
668 return rc;
675 int rc;
690 rc = cxl_internal_send_cmd(mds, &mbox_cmd);
691 if (rc < 0) {
693 rc);
694 return rc;
705 int rc;
707 rc = cxl_event_config_msgnums(mds, &policy);
708 if (rc)
709 return rc;
711 rc = cxl_event_req_irq(cxlds, policy.info_settings);
712 if (rc) {
714 return rc;
717 rc = cxl_event_req_irq(cxlds, policy.warn_settings);
718 if (rc) {
720 return rc;
723 rc = cxl_event_req_irq(cxlds, policy.failure_settings);
724 if (rc) {
726 return rc;
729 rc = cxl_event_req_irq(cxlds, policy.fatal_settings);
730 if (rc) {
732 return rc;
749 int rc;
763 rc = cxl_mem_alloc_event_buf(mds);
764 if (rc)
765 return rc;
767 rc = cxl_event_get_int_policy(mds, &policy);
768 if (rc)
769 return rc;
780 rc = cxl_event_irqsetup(mds);
781 if (rc)
782 return rc;
796 int i, rc, pmu_count;
806 rc = pcim_enable_device(pdev);
807 if (rc)
808 return rc;
825 rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map);
826 if (rc)
827 return rc;
829 rc = cxl_map_device_regs(&map, &cxlds->regs.device_regs);
830 if (rc)
831 return rc;
837 rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT,
839 if (rc)
840 dev_warn(&pdev->dev, "No component registers (%d)\n", rc);
844 rc = cxl_map_component_regs(&cxlds->reg_map, &cxlds->regs.component,
846 if (rc)
849 rc = cxl_await_media_ready(cxlds);
850 if (rc == 0)
853 dev_warn(&pdev->dev, "Media not active (%d)\n", rc);
857 rc = cxl_pci_setup_mailbox(mds, irq_avail);
858 if (rc)
859 return rc;
861 rc = cxl_enumerate_cmds(mds);
862 if (rc)
863 return rc;
865 rc = cxl_set_timestamp(mds);
866 if (rc)
867 return rc;
869 rc = cxl_poison_state_init(mds);
870 if (rc)
871 return rc;
873 rc = cxl_dev_state_identify(mds);
874 if (rc)
875 return rc;
877 rc = cxl_mem_create_range_info(mds);
878 if (rc)
879 return rc;
885 rc = devm_cxl_setup_fw_upload(&pdev->dev, mds);
886 if (rc)
887 return rc;
889 rc = devm_cxl_sanitize_setup_notifier(&pdev->dev, cxlmd);
890 if (rc)
891 return rc;
897 rc = cxl_find_regblock_instance(pdev, CXL_REGLOC_RBI_PMU, &map, i);
898 if (rc) {
903 rc = cxl_map_pmu_regs(&map, &pmu_regs);
904 if (rc) {
909 rc = devm_cxl_pmu_add(cxlds->dev, &pmu_regs, cxlmd->id, i, CXL_PMU_MEMDEV);
910 if (rc) {
916 rc = cxl_event_config(host_bridge, mds, irq_avail);
917 if (rc)
918 return rc;
920 rc = cxl_pci_ras_unmask(pdev);
921 if (rc)
926 return rc;