drivers/cxl/pci.c

22  * This implements the PCI exclusive functionality for a CXL device as it is
23  * defined by the Compute Express Link specification. CXL devices may surface
24  * certain functionality even if it isn't CXL enabled. While this driver is
25  * focused around the PCI specific aspects of a CXL device, it binds to the
26  * specific CXL memory device class code, and therefore the implementation of
27  * cxl_pci is focused around CXL memory devices.
30  *  - Create the memX device and register on the CXL bus.
33  *  - Registers a CXL mailbox with cxl_core.
40 /* CXL 2.0 - 8.2.8.4 */
44  * CXL 2.0 ECN "Add Mailbox Ready Time" defines a capability field to
50  * until someone builds a CXL device that needs more time in practice.
183  * This is a generic form of the CXL mailbox send command thus only using the
184  * registers defined by the mailbox capability ID - CXL 2.0 8.2.8.4. Memory
185  * devices, and perhaps other types of CXL devices may have further information
189  * The CXL spec allows for up to two mailboxes. The intention is for the primary
208 	 * Here are the steps from 8.2.8.4 of the CXL 2.0 spec.
425 	 * CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register
465  * Assume that any RCIEP that emits the CXL memory expander class code
596 	 * Per CXL 3.0 3.1.1 CXL.io Endpoint a function on a CXL device must
598 	 * CXL.cache or CXL.mem.
622 		 * CXL 3.0 8.2.8.3.1: The lower 32 bits are the status;
752 	 * When BIOS maintains CXL error reporting control, it will process
823 			 "Device DVSEC not present, skip CXL.mem init\n");
930 	/* PCI class code for CXL.mem Type-3 Devices */
942 	dev_info(&pdev->dev, "%s: restart CXL.mem after slot reset\n",
1048 MODULE_IMPORT_NS(CXL);