Lines Matching defs:offset
47 * CXL.cache and CXL.mem registers are at offset 0x1000 as defined in
66 u16 cap_id, offset;
72 offset = FIELD_GET(CXL_CM_CAP_PTR_MASK, hdr);
73 register_block = base + offset;
82 offset);
91 offset);
97 offset);
105 rmap->offset = CXL_CM_OFFSET + offset;
136 u32 offset, length;
141 offset = readl(base + cap * 0x10 + 0x4);
147 dev_dbg(dev, "found Status capability (0x%x)\n", offset);
151 dev_dbg(dev, "found Mailbox capability (0x%x)\n", offset);
155 dev_dbg(dev, "found Secondary Mailbox capability (0x%x)\n", offset);
158 dev_dbg(dev, "found Memory Device capability (0x%x)\n", offset);
163 dev_dbg(dev, "Vendor cap ID: %#x offset: %#x\n", cap_id, offset);
165 dev_dbg(dev, "Unknown cap ID: %#x offset: %#x\n", cap_id, offset);
173 rmap->offset = offset;
226 addr = map->resource + mi->rmap->offset;
260 addr = phys_addr + mi->rmap->offset;
276 u64 offset = ((u64)reg_hi << 32) |
279 if (offset > pci_resource_len(pdev, bar)) {
281 "BAR%d: %pr: too small (offset: %pa, type: %d)\n", bar,
282 &pdev->resource[bar], &offset, reg_type);
287 map->resource = pci_resource_start(pdev, bar) + offset;
288 map->max_size = pci_resource_len(pdev, bar) - offset;
476 u16 offset = 0;
489 cap_hdr = readl(addr + offset);
491 offset = PCI_EXT_CAP_NEXT(cap_hdr);
494 if (!offset)
496 cap_hdr = readl(addr + offset);
499 if (offset)
500 dev_dbg(dev, "found AER extended capability (0x%x)\n", offset);
506 return offset;