Lines Matching defs:in
25 * with the CXL core via these interfaces in order to be able to participate in
901 * devm_cxl_add_port - register a cxl_port in CXL memory decode hierarchy
905 * @parent_dport: next hop up in the CXL memory decode hierarchy
1071 * port lock in that case.
1147 dev_warn(dport_dev, "Invalid Component Registers in RCRB");
1197 * @port_id: identifier for this dport in a decoder's target list
1228 * @port_id: identifier for this dport in a decoder's target list
1276 * cxl_add_ep - register an endpoint's interest in a port
1372 * downstream switch port in the immediate ancestor switch.
1527 * non-PCI device, in practice, only cxl_test hits this case.
1613 * Skip intermediate port enumeration in the RCH case, there
1614 * are no ports in between a host bridge and an endpoint.
1624 * Scan for and add all cxl_ports in this device's ancestry.
1636 * The terminal "grandparent" in PCI is NULL and @platform_bus
1661 * If the endpoint already exists in the port's list,
1663 * Otherwise, retry in add_port_attach_ep() after taking
1937 * in the PCIe Link Capabilities structure.
1993 * in the PCIe Link Capabilities structure.
2165 struct access_coordinate *in)
2168 out[i] = in[i];
2177 * cxl_endpoint_get_perf_coordinates - Retrieve performance numbers stored in dports