cxl/core/port.c

154 		struct cxl_dport *dport = cxlsd->target[i];
157 		if (!dport)
162 		rc = sysfs_emit_at(buf, offset, "%d%s", dport->port_id,
778 static int cxl_dport_setup_regs(struct device *host, struct cxl_dport *dport,
783 	if (dev_is_platform(dport->dport_dev))
787 	 * use @dport->dport_dev for the context for error messages during
791 	rc = cxl_setup_comp_regs(dport->dport_dev, &dport->reg_map,
793 	dport->reg_map.host = host;
801 	struct cxl_dport *dport = data;
803 	if (dport->rch)
804 		return einj_cxl_inject_rch_error(dport->rcrb.base, type);
806 	return einj_cxl_inject_error(to_pci_dev(dport->dport_dev), type);
811 static void cxl_debugfs_create_dport_dir(struct cxl_dport *dport)
820 	 * EINJ expects a dport SBDF to be specified for 2.0 error injection.
822 	if (!dport->rch && !dev_is_pci(dport->dport_dev))
825 	dir = cxl_debugfs_create_dir(dev_name(dport->dport_dev));
827 	debugfs_create_file("einj_inject", 0200, dir, dport,
1032 	struct cxl_dport *dport;
1036 	xa_for_each(&port->dports, index, dport)
1037 		if (dport->port_id == id)
1038 			return dport;
1042 static int add_dport(struct cxl_port *port, struct cxl_dport *dport)
1048 	dup = find_dport(port, dport->port_id);
1051 			"unable to add dport%d-%s non-unique port id (%s)\n",
1052 			dport->port_id, dev_name(dport->dport_dev),
1057 	rc = xa_insert(&port->dports, (unsigned long)dport->dport_dev, dport,
1069  * dport add/remove. Instead, root dports are manually added by a
1087 	struct cxl_dport *dport = data;
1088 	struct cxl_port *port = dport->port;
1090 	xa_erase(&port->dports, (unsigned long) dport->dport_dev);
1091 	put_device(dport->dport_dev);
1096 	struct cxl_dport *dport = data;
1097 	struct cxl_port *port = dport->port;
1100 	sprintf(link_name, "dport%d", dport->port_id);
1110 	struct cxl_dport *dport;
1120 		dev_WARN_ONCE(&port->dev, 1, "dport:%s bad devm context\n",
1125 	if (snprintf(link_name, CXL_TARGET_STRLEN, "dport%d", port_id) >=
1129 	dport = devm_kzalloc(host, sizeof(*dport), GFP_KERNEL);
1130 	if (!dport)
1133 	dport->dport_dev = dport_dev;
1134 	dport->port_id = port_id;
1135 	dport->port = port;
1138 		rc = cxl_dport_setup_regs(&port->dev, dport,
1143 		dport->rcrb.base = rcrb;
1144 		component_reg_phys = __rcrb_to_component(dport_dev, &dport->rcrb,
1152 		 * RCH @dport is not ready to map until associated with its
1155 		rc = cxl_dport_setup_regs(NULL, dport, component_reg_phys);
1159 		dport->rch = true;
1163 		dev_dbg(dport_dev, "Component Registers found for dport: %pa\n",
1167 	rc = add_dport(port, dport);
1173 	rc = devm_add_action_or_reset(host, cxl_dport_remove, dport);
1181 	rc = devm_add_action_or_reset(host, cxl_dport_unlink, dport);
1186 		dport->link_latency = cxl_pci_get_latency(to_pci_dev(dport_dev));
1188 	cxl_debugfs_create_dport_dir(dport);
1190 	return dport;
1195  * @port: the cxl_port that references this dport
1196  * @dport_dev: firmware or PCI device representing the dport
1197  * @port_id: identifier for this dport in a decoder's target list
1208 	struct cxl_dport *dport;
1210 	dport = __devm_cxl_add_dport(port, dport_dev, port_id,
1212 	if (IS_ERR(dport)) {
1213 		dev_dbg(dport_dev, "failed to add dport to %s: %ld\n",
1214 			dev_name(&port->dev), PTR_ERR(dport));
1216 		dev_dbg(dport_dev, "dport added to %s\n",
1220 	return dport;
1226  * @port: the cxl_port that references this dport
1227  * @dport_dev: firmware or PCI device representing the dport
1228  * @port_id: identifier for this dport in a decoder's target list
1237 	struct cxl_dport *dport;
1240 		dev_dbg(&port->dev, "failed to add RCH dport, missing RCRB\n");
1244 	dport = __devm_cxl_add_dport(port, dport_dev, port_id,
1246 	if (IS_ERR(dport)) {
1247 		dev_dbg(dport_dev, "failed to add RCH dport to %s: %ld\n",
1248 			dev_name(&port->dev), PTR_ERR(dport));
1250 		dev_dbg(dport_dev, "RCH dport added to %s\n",
1254 	return dport;
1260 	struct cxl_port *port = new->dport->port;
1277  * @dport: the dport that routes to @ep_dev
1284 static int cxl_add_ep(struct cxl_dport *dport, struct device *ep_dev)
1294 	ep->dport = dport;
1305 	struct cxl_dport **dport;
1311 	struct cxl_dport *dport;
1320 	dport = cxl_find_dport_by_dev(port, ctx->dport_dev);
1321 	if (ctx->dport)
1322 		*ctx->dport = dport;
1323 	return dport != NULL;
1340 				      struct cxl_dport **dport)
1344 		.dport = dport,
1354 					 struct cxl_dport **dport)
1359 		.dport = dport,
1438 	struct cxl_dport *dport;
1443 	xa_for_each(&port->dports, index, dport) {
1444 		devm_release_action(&port->dev, cxl_dport_unlink, dport);
1445 		devm_release_action(&port->dev, cxl_dport_remove, dport);
1446 		devm_kfree(&port->dev, dport);
1544 	struct cxl_dport *dport, *parent_dport;
1554 		dev_dbg(&cxlmd->dev, "%s is a root dport\n",
1574 	port = find_cxl_port_at(parent_port, dport_dev, &dport);
1579 		/* retry find to pick up the new dport information */
1581 			port = find_cxl_port_at(parent_port, dport_dev, &dport);
1591 		rc = cxl_add_ep(dport, &cxlmd->dev);
1632 		struct cxl_dport *dport;
1644 			dev_warn(dev, "at %s no parent for dport: %s\n",
1652 		port = find_cxl_port(dport_dev, &dport);
1658 			rc = cxl_add_ep(dport, &cxlmd->dev);
1698 				   struct cxl_dport **dport)
1700 	return find_cxl_port(pdev->dev.parent, dport);
1705 				   struct cxl_dport **dport)
1707 	return find_cxl_port(grandparent(&cxlmd->dev), dport);
1726 		struct cxl_dport *dport = find_dport(port, target_map[i]);
1728 		if (!dport)
1730 		cxlsd->target[i] = dport;
2199 	struct cxl_dport *dport;
2222 		dport = iter->parent_dport;
2231 			if (!coordinates_valid(dport->coord))
2233 			cxl_coordinates_combine(c, c, dport->coord);
2235 		add_latency(c, dport->link_latency);
2238 	dport = iter->parent_dport;
2240 	if (!coordinates_valid(dport->coord))
2242 	cxl_coordinates_combine(c, c, dport->coord);