cxl/core/port.c

22  * The CXL core provides a set of interfaces that can be consumed by CXL aware
24  * regions, memory devices, ports, and decoders. CXL aware drivers must register
25  * with the CXL core via these interfaces in order to be able to participate in
26  * cross-device interleave coordination. The CXL core also establishes and
29  * CXL core introduces sysfs hierarchy to control the devices that are
440 EXPORT_SYMBOL_NS_GPL(to_cxl_root_decoder, CXL);
474 EXPORT_SYMBOL_NS_GPL(is_endpoint_decoder, CXL);
480 EXPORT_SYMBOL_NS_GPL(is_root_decoder, CXL);
486 EXPORT_SYMBOL_NS_GPL(is_switch_decoder, CXL);
496 EXPORT_SYMBOL_NS_GPL(to_cxl_decoder, CXL);
505 EXPORT_SYMBOL_NS_GPL(to_cxl_endpoint_decoder, CXL);
514 EXPORT_SYMBOL_NS_GPL(to_cxl_switch_decoder, CXL);
588 EXPORT_SYMBOL_NS_GPL(is_cxl_port, CXL);
597 EXPORT_SYMBOL_NS_GPL(to_cxl_port, CXL);
611 	 * CXL root port's and the first level of ports are unregistered
819 	 * dport_dev needs to be a PCIe port for CXL 2.0+ ports because
901  * devm_cxl_add_port - register a cxl_port in CXL memory decode hierarchy
905  * @parent_dport: next hop up in the CXL memory decode hierarchy
934 EXPORT_SYMBOL_NS_GPL(devm_cxl_add_port, CXL);
950 EXPORT_SYMBOL_NS_GPL(devm_cxl_add_root, CXL);
954 	/* There is no pci_bus associated with a CXL platform-root port */
966 EXPORT_SYMBOL_NS_GPL(cxl_port_to_pci_bus, CXL);
987 EXPORT_SYMBOL_NS_GPL(devm_cxl_register_pci_bus, CXL);
1019 EXPORT_SYMBOL_NS_GPL(find_cxl_root, CXL);
1028 EXPORT_SYMBOL_NS_GPL(put_cxl_root, CXL);
1067  * Since root-level CXL dports cannot be enumerated by PCI they are not
1198  * @component_reg_phys: optional location of CXL component registers
1222 EXPORT_SYMBOL_NS_GPL(devm_cxl_add_dport, CXL);
1231  * See CXL 3.0 9.11.8 CXL Devices Attached to an RCH
1256 EXPORT_SYMBOL_NS_GPL(devm_cxl_add_rch_dport, CXL);
1280  * Intermediate CXL ports are scanned based on the arrival of endpoints.
1418 EXPORT_SYMBOL_NS_GPL(cxl_endpoint_autoremove, CXL);
1526 	 * Theoretically, CXL component registers can be hosted on a
1551 		 * CXL-root 'cxl_port' on a previous iteration, fail for now to
1568 			 "port %s:%s disabled, failed to enumerate CXL.mem\n",
1695 EXPORT_SYMBOL_NS_GPL(devm_cxl_enumerate_ports, CXL);
1702 EXPORT_SYMBOL_NS_GPL(cxl_pci_find_port, CXL);
1709 EXPORT_SYMBOL_NS_GPL(cxl_mem_find_port, CXL);
1749 EXPORT_SYMBOL_NS_GPL(cxl_hb_modulo, CXL);
1759  * enable some address space for CXL.mem utilization. A decoder is
1808  * @port: owning CXL root of this decoder
1813  * 'CXL root' decoder is one that decodes from a top-level / static platform
1814  * firmware description of CXL resources into a CXL standard decode
1861 EXPORT_SYMBOL_NS_GPL(cxl_root_decoder_alloc, CXL);
1865  * @port: owning CXL switch port of this decoder
1898 EXPORT_SYMBOL_NS_GPL(cxl_switch_decoder_alloc, CXL);
1930 EXPORT_SYMBOL_NS_GPL(cxl_endpoint_decoder_alloc, CXL);
1986 EXPORT_SYMBOL_NS_GPL(cxl_decoder_add_locked, CXL);
2020 EXPORT_SYMBOL_NS_GPL(cxl_decoder_add, CXL);
2038 EXPORT_SYMBOL_NS_GPL(cxl_decoder_autoremove, CXL);
2071 EXPORT_SYMBOL_NS_GPL(__cxl_driver_register, CXL);
2077 EXPORT_SYMBOL_NS_GPL(cxl_driver_unregister, CXL);
2113 	pr_debug("CXL bus rescan result: %d\n", rc);
2122 EXPORT_SYMBOL_NS_GPL(cxl_bus_rescan, CXL);
2128 EXPORT_SYMBOL_NS_GPL(cxl_bus_drain, CXL);
2134 EXPORT_SYMBOL_NS_GPL(schedule_cxl_memdev_detach, CXL);
2178  *				   of CXL path
2218 	 * latency of the CXL link from the current device/port to the connected
2260 EXPORT_SYMBOL_NS_GPL(cxl_endpoint_get_perf_coordinates, CXL);
2297 EXPORT_SYMBOL_NS_GPL(cxl_bus_type, CXL);
2305 EXPORT_SYMBOL_NS_GPL(cxl_debugfs_create_dir, CXL);
2360 MODULE_IMPORT_NS(CXL);