cxl/core/pci.c

41 	struct cxl_dport *dport;
60 	dport = devm_cxl_add_dport(port, &pdev->dev, port_num, map.resource);
61 	if (IS_ERR(dport)) {
62 		ctx->error = PTR_ERR(dport);
63 		return PTR_ERR(dport);
773 static void cxl_dport_map_rch_aer(struct cxl_dport *dport)
775 	struct cxl_rcrb_info *ri = &dport->rcrb;
780 	if (dport->rch && ri->aer_cap) {
781 		host = dport->reg_map.host;
787 	dport->regs.dport_aer = dport_aer;
790 static void cxl_dport_map_regs(struct cxl_dport *dport)
792 	struct cxl_register_map *map = &dport->reg_map;
793 	struct device *dev = dport->dport_dev;
797 	else if (cxl_map_component_regs(map, &dport->regs.component,
801 	if (dport->rch)
802 		cxl_dport_map_rch_aer(dport);
805 static void cxl_disable_rch_root_ints(struct cxl_dport *dport)
807 	void __iomem *aer_base = dport->regs.dport_aer;
814 	bridge = to_pci_host_bridge(dport->dport_dev);
834 void cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport)
836 	struct device *dport_dev = dport->dport_dev;
841 		dport->rcrb.aer_cap = cxl_rcrb_to_aer(dport_dev, dport->rcrb.base);
843 	dport->reg_map.host = host;
844 	cxl_dport_map_regs(dport);
846 	if (dport->rch)
847 		cxl_disable_rch_root_ints(dport);
852 					  struct cxl_dport *dport)
854 	return __cxl_handle_cor_ras(cxlds, dport->regs.ras);
858 				       struct cxl_dport *dport)
860 	return __cxl_handle_ras(cxlds, dport->regs.ras);
915 	struct cxl_dport *dport;
919 	port = cxl_pci_find_port(pdev, &dport);
925 	if (!cxl_rch_get_aer_info(dport->regs.dport_aer, &aer_regs))
934 		cxl_handle_rdport_cor_ras(cxlds, dport);
936 		cxl_handle_rdport_ras(cxlds, dport);