drivers/crypto/talitos.c

139 static int reset_channel(struct device *dev, int ch)
146 		setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO,
149 		while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR_LO) &
153 		setbits32(priv->chan[ch].reg + TALITOS_CCCR,
156 		while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) &
162 		dev_err(dev, "failed to reset channel %d\n", ch);
167 	setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, TALITOS_CCCR_LO_EAE |
171 		setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO,
176 		setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO,
214 	int ch, err;
232 	for (ch = 0; ch < priv->num_channels; ch++) {
233 		err = reset_channel(dev, ch);
260  * @ch:		the SEC device channel to be used
269 static int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
281 	spin_lock_irqsave(&priv->chan[ch].head_lock, flags);
283 	if (!atomic_inc_not_zero(&priv->chan[ch].submit_count)) {
285 		spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
289 	head = priv->chan[ch].head;
290 	request = &priv->chan[ch].fifo[head];
307 	priv->chan[ch].head = (priv->chan[ch].head + 1) & (priv->fifo_len - 1);
314 	out_be32(priv->chan[ch].reg + TALITOS_FF,
316 	out_be32(priv->chan[ch].reg + TALITOS_FF_LO,
319 	spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
342 static void flush_channel(struct device *dev, int ch, int error, int reset_ch)
350 	spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
352 	tail = priv->chan[ch].tail;
353 	while (priv->chan[ch].fifo[tail].desc) {
356 		request = &priv->chan[ch].fifo[tail];
384 		priv->chan[ch].tail = (tail + 1) & (priv->fifo_len - 1);
386 		spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
388 		atomic_dec(&priv->chan[ch].submit_count);
395 		spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
396 		tail = priv->chan[ch].tail;
399 	spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
429 DEF_TALITOS1_DONE(4ch, TALITOS1_ISR_4CHDONE)
456 DEF_TALITOS2_DONE(4ch, TALITOS2_ISR_4CHDONE)
464 static __be32 current_desc_hdr(struct device *dev, int ch)
470 	cur_desc = ((u64)in_be32(priv->chan[ch].reg + TALITOS_CDPR)) << 32;
471 	cur_desc |= in_be32(priv->chan[ch].reg + TALITOS_CDPR_LO);
478 	tail = priv->chan[ch].tail;
481 	while (priv->chan[ch].fifo[iter].dma_desc != cur_desc &&
482 	       priv->chan[ch].fifo[iter].desc->next_desc != cpu_to_be32(cur_desc)) {
490 	if (priv->chan[ch].fifo[iter].desc->next_desc == cpu_to_be32(cur_desc)) {
493 		edesc = container_of(priv->chan[ch].fifo[iter].desc,
499 	return priv->chan[ch].fifo[iter].desc->hdr;
505 static void report_eu_error(struct device *dev, int ch, __be32 desc_hdr)
511 		desc_hdr = cpu_to_be32(in_be32(priv->chan[ch].reg + TALITOS_DESCBUF));
573 			in_be32(priv->chan[ch].reg + TALITOS_DESCBUF + 8*i),
574 			in_be32(priv->chan[ch].reg + TALITOS_DESCBUF_LO + 8*i));
584 	int ch, error, reset_dev = 0;
589 	for (ch = 0; ch < priv->num_channels; ch++) {
593 			if (!(isr & (1 << (29 + (ch & 1) * 2 - (ch & 2) * 6))))
596 			if (!(isr & (1 << (ch * 2 + 1))))
602 		v_lo = in_be32(priv->chan[ch].reg + TALITOS_CCPSR_LO);
628 			report_eu_error(dev, ch, current_desc_hdr(dev, ch));
640 		flush_channel(dev, ch, error, reset_ch);
643 			reset_channel(dev, ch);
645 			setbits32(priv->chan[ch].reg + TALITOS_CCCR,
647 			setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, 0);
648 			while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) &
653 					ch);
668 		for (ch = 0; ch < priv->num_channels; ch++)
669 			flush_channel(dev, ch, -EIO, 1);
709 DEF_TALITOS1_INTERRUPT(4ch, TALITOS1_ISR_4CHDONE, TALITOS1_ISR_4CHERR, 0)
744 DEF_TALITOS2_INTERRUPT(4ch, TALITOS2_ISR_4CHDONE, TALITOS2_ISR_4CHERR, 0)
852 	int ch;
1308 	ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
1631 	ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
1904 	ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
3058 	ctx->ch = atomic_inc_return(&priv->last_chan) &