Lines Matching refs:cryp
5 * Ux500 support taken from snippets in the old Ux500 cryp driver
27 #define DRIVER_NAME "stm32-cryp"
161 struct stm32_cryp *cryp;
212 static inline bool is_aes(struct stm32_cryp *cryp)
214 return cryp->flags & FLG_AES;
217 static inline bool is_des(struct stm32_cryp *cryp)
219 return cryp->flags & FLG_DES;
222 static inline bool is_tdes(struct stm32_cryp *cryp)
224 return cryp->flags & FLG_TDES;
227 static inline bool is_ecb(struct stm32_cryp *cryp)
229 return cryp->flags & FLG_ECB;
232 static inline bool is_cbc(struct stm32_cryp *cryp)
234 return cryp->flags & FLG_CBC;
237 static inline bool is_ctr(struct stm32_cryp *cryp)
239 return cryp->flags & FLG_CTR;
242 static inline bool is_gcm(struct stm32_cryp *cryp)
244 return cryp->flags & FLG_GCM;
247 static inline bool is_ccm(struct stm32_cryp *cryp)
249 return cryp->flags & FLG_CCM;
252 static inline bool is_encrypt(struct stm32_cryp *cryp)
254 return cryp->flags & FLG_ENCRYPT;
257 static inline bool is_decrypt(struct stm32_cryp *cryp)
259 return !is_encrypt(cryp);
262 static inline u32 stm32_cryp_read(struct stm32_cryp *cryp, u32 ofst)
264 return readl_relaxed(cryp->regs + ofst);
267 static inline void stm32_cryp_write(struct stm32_cryp *cryp, u32 ofst, u32 val)
269 writel_relaxed(val, cryp->regs + ofst);
272 static inline int stm32_cryp_wait_busy(struct stm32_cryp *cryp)
276 return readl_relaxed_poll_timeout(cryp->regs + cryp->caps->sr, status,
280 static inline void stm32_cryp_enable(struct stm32_cryp *cryp)
282 writel_relaxed(readl_relaxed(cryp->regs + cryp->caps->cr) | CR_CRYPEN,
283 cryp->regs + cryp->caps->cr);
286 static inline int stm32_cryp_wait_enable(struct stm32_cryp *cryp)
290 return readl_relaxed_poll_timeout(cryp->regs + cryp->caps->cr, status,
294 static inline int stm32_cryp_wait_output(struct stm32_cryp *cryp)
298 return readl_relaxed_poll_timeout(cryp->regs + cryp->caps->sr, status,
302 static inline void stm32_cryp_key_read_enable(struct stm32_cryp *cryp)
304 writel_relaxed(readl_relaxed(cryp->regs + cryp->caps->cr) | CR_KEYRDEN,
305 cryp->regs + cryp->caps->cr);
308 static inline void stm32_cryp_key_read_disable(struct stm32_cryp *cryp)
310 writel_relaxed(readl_relaxed(cryp->regs + cryp->caps->cr) & ~CR_KEYRDEN,
311 cryp->regs + cryp->caps->cr);
314 static int stm32_cryp_read_auth_tag(struct stm32_cryp *cryp);
315 static void stm32_cryp_finish_req(struct stm32_cryp *cryp, int err);
319 struct stm32_cryp *tmp, *cryp = NULL;
322 if (!ctx->cryp) {
324 cryp = tmp;
327 ctx->cryp = cryp;
329 cryp = ctx->cryp;
334 return cryp;
337 static void stm32_cryp_hw_write_iv(struct stm32_cryp *cryp, __be32 *iv)
342 stm32_cryp_write(cryp, cryp->caps->iv0l, be32_to_cpu(*iv++));
343 stm32_cryp_write(cryp, cryp->caps->iv0r, be32_to_cpu(*iv++));
345 if (is_aes(cryp)) {
346 stm32_cryp_write(cryp, cryp->caps->iv1l, be32_to_cpu(*iv++));
347 stm32_cryp_write(cryp, cryp->caps->iv1r, be32_to_cpu(*iv++));
351 static void stm32_cryp_get_iv(struct stm32_cryp *cryp)
353 struct skcipher_request *req = cryp->req;
359 if (cryp->caps->iv_protection)
360 stm32_cryp_key_read_enable(cryp);
362 *tmp++ = cpu_to_be32(stm32_cryp_read(cryp, cryp->caps->iv0l));
363 *tmp++ = cpu_to_be32(stm32_cryp_read(cryp, cryp->caps->iv0r));
365 if (is_aes(cryp)) {
366 *tmp++ = cpu_to_be32(stm32_cryp_read(cryp, cryp->caps->iv1l));
367 *tmp++ = cpu_to_be32(stm32_cryp_read(cryp, cryp->caps->iv1r));
370 if (cryp->caps->iv_protection)
371 stm32_cryp_key_read_disable(cryp);
493 static u32 stm32_cryp_get_hw_mode(struct stm32_cryp *cryp)
495 if (is_aes(cryp) && is_ecb(cryp))
498 if (is_aes(cryp) && is_cbc(cryp))
501 if (is_aes(cryp) && is_ctr(cryp))
504 if (is_aes(cryp) && is_gcm(cryp))
507 if (is_aes(cryp) && is_ccm(cryp))
510 if (is_des(cryp) && is_ecb(cryp))
513 if (is_des(cryp) && is_cbc(cryp))
516 if (is_tdes(cryp) && is_ecb(cryp))
519 if (is_tdes(cryp) && is_cbc(cryp))
522 dev_err(cryp->dev, "Unknown mode\n");
526 static unsigned int stm32_cryp_get_input_text_len(struct stm32_cryp *cryp)
528 return is_encrypt(cryp) ? cryp->areq->cryptlen :
529 cryp->areq->cryptlen - cryp->authsize;
532 static int stm32_cryp_gcm_init(struct stm32_cryp *cryp, u32 cfg)
538 memcpy(iv, cryp->areq->iv, 12);
540 cryp->gcm_ctr = GCM_CTR_INIT;
541 stm32_cryp_hw_write_iv(cryp, iv);
543 stm32_cryp_write(cryp, cryp->caps->cr, cfg | CR_PH_INIT | CR_CRYPEN);
546 ret = stm32_cryp_wait_enable(cryp);
548 dev_err(cryp->dev, "Timeout (gcm init)\n");
553 if (cryp->areq->assoclen) {
555 stm32_cryp_write(cryp, cryp->caps->cr, cfg);
556 } else if (stm32_cryp_get_input_text_len(cryp)) {
558 stm32_cryp_write(cryp, cryp->caps->cr, cfg);
564 static void stm32_crypt_gcmccm_end_header(struct stm32_cryp *cryp)
570 if (!cryp->header_in) {
572 err = stm32_cryp_wait_busy(cryp);
574 dev_err(cryp->dev, "Timeout (gcm/ccm header)\n");
575 stm32_cryp_write(cryp, cryp->caps->imsc, 0);
576 stm32_cryp_finish_req(cryp, err);
580 if (stm32_cryp_get_input_text_len(cryp)) {
582 cfg = stm32_cryp_read(cryp, cryp->caps->cr);
584 stm32_cryp_write(cryp, cryp->caps->cr, cfg);
588 stm32_cryp_write(cryp, cryp->caps->cr, cfg);
599 static void stm32_cryp_write_ccm_first_header(struct stm32_cryp *cryp)
603 u32 alen = cryp->areq->assoclen;
625 scatterwalk_copychunks((char *)block + len, &cryp->in_walk, written, 0);
627 writesl(cryp->regs + cryp->caps->din, block, AES_BLOCK_32);
629 cryp->header_in -= written;
631 stm32_crypt_gcmccm_end_header(cryp);
634 static int stm32_cryp_ccm_init(struct stm32_cryp *cryp, u32 cfg)
644 memcpy(iv, cryp->areq->iv, AES_BLOCK_SIZE);
647 stm32_cryp_hw_write_iv(cryp, (__be32 *)iv);
652 b0[0] |= (8 * ((cryp->authsize - 2) / 2));
654 if (cryp->areq->assoclen)
657 textlen = stm32_cryp_get_input_text_len(cryp);
663 stm32_cryp_write(cryp, cryp->caps->cr, cfg | CR_PH_INIT | CR_CRYPEN);
672 if (!cryp->caps->padding_wa)
674 stm32_cryp_write(cryp, cryp->caps->din, xd);
678 ret = stm32_cryp_wait_enable(cryp);
680 dev_err(cryp->dev, "Timeout (ccm init)\n");
685 if (cryp->areq->assoclen) {
687 stm32_cryp_write(cryp, cryp->caps->cr, cfg);
690 stm32_cryp_write_ccm_first_header(cryp);
691 } else if (stm32_cryp_get_input_text_len(cryp)) {
693 stm32_cryp_write(cryp, cryp->caps->cr, cfg);
699 static int stm32_cryp_hw_init(struct stm32_cryp *cryp)
704 pm_runtime_get_sync(cryp->dev);
707 stm32_cryp_write(cryp, cryp->caps->imsc, 0);
712 switch (cryp->ctx->keylen) {
727 hw_mode = stm32_cryp_get_hw_mode(cryp);
732 if (is_decrypt(cryp) &&
735 if (cryp->caps->kp_mode)
736 stm32_cryp_write(cryp, cryp->caps->cr,
739 stm32_cryp_write(cryp,
740 cryp->caps->cr, cfg | CR_AES_ECB | CR_KSE);
743 stm32_cryp_hw_write_key(cryp);
746 stm32_cryp_enable(cryp);
748 ret = stm32_cryp_wait_busy(cryp);
750 dev_err(cryp->dev, "Timeout (key preparation)\n");
757 stm32_cryp_write(cryp, cryp->caps->cr, cfg);
760 if (is_decrypt(cryp))
764 stm32_cryp_write(cryp, cryp->caps->cr, cfg);
767 stm32_cryp_hw_write_key(cryp);
775 ret = stm32_cryp_ccm_init(cryp, cfg);
777 ret = stm32_cryp_gcm_init(cryp, cfg);
788 stm32_cryp_hw_write_iv(cryp, (__be32 *)cryp->req->iv);
796 stm32_cryp_enable(cryp);
801 static void stm32_cryp_finish_req(struct stm32_cryp *cryp, int err)
803 if (!err && (is_gcm(cryp) || is_ccm(cryp)))
805 err = stm32_cryp_read_auth_tag(cryp);
807 if (!err && (!(is_gcm(cryp) || is_ccm(cryp) || is_ecb(cryp))))
808 stm32_cryp_get_iv(cryp);
810 pm_runtime_mark_last_busy(cryp->dev);
811 pm_runtime_put_autosuspend(cryp->dev);
813 if (is_gcm(cryp) || is_ccm(cryp))
814 crypto_finalize_aead_request(cryp->engine, cryp->areq, err);
816 crypto_finalize_skcipher_request(cryp->engine, cryp->req,
820 static int stm32_cryp_cpu_start(struct stm32_cryp *cryp)
823 stm32_cryp_write(cryp, cryp->caps->imsc, IMSCR_IN | IMSCR_OUT);
851 struct stm32_cryp *cryp = stm32_cryp_find_dev(ctx);
853 if (!cryp)
858 return crypto_transfer_skcipher_request_to_engine(cryp->engine, req);
865 struct stm32_cryp *cryp = stm32_cryp_find_dev(ctx);
867 if (!cryp)
872 return crypto_transfer_aead_request_to_engine(cryp->engine, req);
1156 struct stm32_cryp *cryp;
1167 cryp = ctx->cryp;
1172 ctx->cryp = cryp;
1174 cryp->flags = (cryp->flags & ~FLG_MODE_MASK) | rctx->mode;
1175 cryp->hw_blocksize = is_aes(cryp) ? AES_BLOCK_SIZE : DES_BLOCK_SIZE;
1176 cryp->ctx = ctx;
1179 cryp->req = req;
1180 cryp->areq = NULL;
1181 cryp->header_in = 0;
1182 cryp->payload_in = req->cryptlen;
1183 cryp->payload_out = req->cryptlen;
1184 cryp->authsize = 0;
1202 cryp->areq = areq;
1203 cryp->req = NULL;
1204 cryp->authsize = crypto_aead_authsize(crypto_aead_reqtfm(areq));
1205 if (is_encrypt(cryp)) {
1206 cryp->payload_in = areq->cryptlen;
1207 cryp->header_in = areq->assoclen;
1208 cryp->payload_out = areq->cryptlen;
1210 cryp->payload_in = areq->cryptlen - cryp->authsize;
1211 cryp->header_in = areq->assoclen;
1212 cryp->payload_out = cryp->payload_in;
1217 scatterwalk_start(&cryp->in_walk, in_sg);
1219 cryp->out_sg = req ? req->dst : areq->dst;
1220 scatterwalk_start(&cryp->out_walk, cryp->out_sg);
1222 if (is_gcm(cryp) || is_ccm(cryp)) {
1224 scatterwalk_copychunks(NULL, &cryp->out_walk, cryp->areq->assoclen, 2);
1227 if (is_ctr(cryp))
1228 memset(cryp->last_ctr, 0, sizeof(cryp->last_ctr));
1230 ret = stm32_cryp_hw_init(cryp);
1241 struct stm32_cryp *cryp = ctx->cryp;
1243 if (!cryp)
1247 stm32_cryp_cpu_start(cryp);
1255 struct stm32_cryp *cryp = ctx->cryp;
1258 if (!cryp)
1265 if (unlikely(!cryp->payload_in && !cryp->header_in)) {
1267 stm32_cryp_finish_req(cryp, 0);
1271 return stm32_cryp_cpu_start(cryp);
1274 static int stm32_cryp_read_auth_tag(struct stm32_cryp *cryp)
1281 cfg = stm32_cryp_read(cryp, cryp->caps->cr);
1288 stm32_cryp_write(cryp, cryp->caps->cr, cfg);
1290 if (is_gcm(cryp)) {
1292 size_bit = cryp->areq->assoclen * 8;
1293 if (cryp->caps->swap_final)
1296 stm32_cryp_write(cryp, cryp->caps->din, 0);
1297 stm32_cryp_write(cryp, cryp->caps->din, size_bit);
1299 size_bit = is_encrypt(cryp) ? cryp->areq->cryptlen :
1300 cryp->areq->cryptlen - cryp->authsize;
1302 if (cryp->caps->swap_final)
1305 stm32_cryp_write(cryp, cryp->caps->din, 0);
1306 stm32_cryp_write(cryp, cryp->caps->din, size_bit);
1313 memcpy(iv, cryp->areq->iv, AES_BLOCK_SIZE);
1319 if (!cryp->caps->padding_wa)
1321 stm32_cryp_write(cryp, cryp->caps->din, xiv);
1326 ret = stm32_cryp_wait_output(cryp);
1328 dev_err(cryp->dev, "Timeout (read tag)\n");
1332 if (is_encrypt(cryp)) {
1336 readsl(cryp->regs + cryp->caps->dout, out_tag, AES_BLOCK_32);
1337 scatterwalk_copychunks(out_tag, &cryp->out_walk, cryp->authsize, 1);
1342 scatterwalk_copychunks(in_tag, &cryp->in_walk, cryp->authsize, 0);
1343 readsl(cryp->regs + cryp->caps->dout, out_tag, AES_BLOCK_32);
1345 if (crypto_memneq(in_tag, out_tag, cryp->authsize))
1349 /* Disable cryp */
1351 stm32_cryp_write(cryp, cryp->caps->cr, cfg);
1356 static void stm32_cryp_check_ctr_counter(struct stm32_cryp *cryp)
1360 if (unlikely(cryp->last_ctr[3] == cpu_to_be32(0xFFFFFFFF))) {
1365 crypto_inc((u8 *)cryp->last_ctr, sizeof(cryp->last_ctr));
1367 cr = stm32_cryp_read(cryp, cryp->caps->cr);
1368 stm32_cryp_write(cryp, cryp->caps->cr, cr & ~CR_CRYPEN);
1370 stm32_cryp_hw_write_iv(cryp, cryp->last_ctr);
1372 stm32_cryp_write(cryp, cryp->caps->cr, cr);
1376 cryp->last_ctr[0] = cpu_to_be32(stm32_cryp_read(cryp, cryp->caps->iv0l));
1377 cryp->last_ctr[1] = cpu_to_be32(stm32_cryp_read(cryp, cryp->caps->iv0r));
1378 cryp->last_ctr[2] = cpu_to_be32(stm32_cryp_read(cryp, cryp->caps->iv1l));
1379 cryp->last_ctr[3] = cpu_to_be32(stm32_cryp_read(cryp, cryp->caps->iv1r));
1382 static void stm32_cryp_irq_read_data(struct stm32_cryp *cryp)
1386 readsl(cryp->regs + cryp->caps->dout, block, cryp->hw_blocksize / sizeof(u32));
1387 scatterwalk_copychunks(block, &cryp->out_walk, min_t(size_t, cryp->hw_blocksize,
1388 cryp->payload_out), 1);
1389 cryp->payload_out -= min_t(size_t, cryp->hw_blocksize,
1390 cryp->payload_out);
1393 static void stm32_cryp_irq_write_block(struct stm32_cryp *cryp)
1397 scatterwalk_copychunks(block, &cryp->in_walk, min_t(size_t, cryp->hw_blocksize,
1398 cryp->payload_in), 0);
1399 writesl(cryp->regs + cryp->caps->din, block, cryp->hw_blocksize / sizeof(u32));
1400 cryp->payload_in -= min_t(size_t, cryp->hw_blocksize, cryp->payload_in);
1403 static void stm32_cryp_irq_write_gcm_padded_data(struct stm32_cryp *cryp)
1412 stm32_cryp_write(cryp, cryp->caps->imsc, 0);
1413 cfg = stm32_cryp_read(cryp, cryp->caps->cr);
1415 stm32_cryp_write(cryp, cryp->caps->cr, cfg);
1418 stm32_cryp_write(cryp, cryp->caps->iv1r, cryp->gcm_ctr - 2);
1423 stm32_cryp_write(cryp, cryp->caps->cr, cfg);
1427 stm32_cryp_write(cryp, cryp->caps->cr, cfg);
1430 stm32_cryp_irq_write_block(cryp);
1432 err = stm32_cryp_wait_output(cryp);
1434 dev_err(cryp->dev, "Timeout (write gcm last data)\n");
1435 return stm32_cryp_finish_req(cryp, err);
1443 readsl(cryp->regs + cryp->caps->dout, block, cryp->hw_blocksize / sizeof(u32));
1445 scatterwalk_copychunks(block, &cryp->out_walk, min_t(size_t, cryp->hw_blocksize,
1446 cryp->payload_out), 1);
1447 cryp->payload_out -= min_t(size_t, cryp->hw_blocksize,
1448 cryp->payload_out);
1453 stm32_cryp_write(cryp, cryp->caps->cr, cfg);
1458 stm32_cryp_write(cryp, cryp->caps->cr, cfg);
1461 writesl(cryp->regs + cryp->caps->din, block, AES_BLOCK_32);
1464 err = stm32_cryp_wait_output(cryp);
1466 dev_err(cryp->dev, "Timeout (write gcm padded data)\n");
1467 return stm32_cryp_finish_req(cryp, err);
1471 stm32_cryp_read(cryp, cryp->caps->dout);
1474 stm32_cryp_finish_req(cryp, 0);
1477 static void stm32_cryp_irq_set_npblb(struct stm32_cryp *cryp)
1482 cfg = stm32_cryp_read(cryp, cryp->caps->cr);
1484 stm32_cryp_write(cryp, cryp->caps->cr, cfg);
1486 cfg |= (cryp->hw_blocksize - cryp->payload_in) << CR_NBPBL_SHIFT;
1488 stm32_cryp_write(cryp, cryp->caps->cr, cfg);
1491 static void stm32_cryp_irq_write_ccm_padded_data(struct stm32_cryp *cryp)
1502 stm32_cryp_write(cryp, cryp->caps->imsc, 0);
1504 cfg = stm32_cryp_read(cryp, cryp->caps->cr);
1506 stm32_cryp_write(cryp, cryp->caps->cr, cfg);
1509 iv1tmp = stm32_cryp_read(cryp, CRYP_CSGCMCCM0R + 7 * 4);
1513 cstmp1[i] = stm32_cryp_read(cryp, CRYP_CSGCMCCM0R + i * 4);
1516 stm32_cryp_write(cryp, cryp->caps->iv1r, iv1tmp);
1521 stm32_cryp_write(cryp, cryp->caps->cr, cfg);
1525 stm32_cryp_write(cryp, cryp->caps->cr, cfg);
1528 stm32_cryp_irq_write_block(cryp);
1530 err = stm32_cryp_wait_output(cryp);
1532 dev_err(cryp->dev, "Timeout (write ccm padded data)\n");
1533 return stm32_cryp_finish_req(cryp, err);
1541 readsl(cryp->regs + cryp->caps->dout, block, cryp->hw_blocksize / sizeof(u32));
1543 scatterwalk_copychunks(block, &cryp->out_walk, min_t(size_t, cryp->hw_blocksize,
1544 cryp->payload_out), 1);
1545 cryp->payload_out -= min_t(size_t, cryp->hw_blocksize, cryp->payload_out);
1549 cstmp2[i] = stm32_cryp_read(cryp, CRYP_CSGCMCCM0R + i * 4);
1554 stm32_cryp_write(cryp, cryp->caps->cr, cfg);
1559 stm32_cryp_write(cryp, cryp->caps->cr, cfg);
1565 stm32_cryp_write(cryp, cryp->caps->din, block[i]);
1569 err = stm32_cryp_wait_busy(cryp);
1571 dev_err(cryp->dev, "Timeout (write ccm padded data)\n");
1574 stm32_cryp_finish_req(cryp, err);
1577 static void stm32_cryp_irq_write_data(struct stm32_cryp *cryp)
1579 if (unlikely(!cryp->payload_in)) {
1580 dev_warn(cryp->dev, "No more data to process\n");
1584 if (unlikely(cryp->payload_in < AES_BLOCK_SIZE &&
1585 (stm32_cryp_get_hw_mode(cryp) == CR_AES_GCM) &&
1586 is_encrypt(cryp))) {
1588 if (cryp->caps->padding_wa) {
1590 stm32_cryp_irq_write_gcm_padded_data(cryp);
1595 stm32_cryp_irq_set_npblb(cryp);
1598 if (unlikely((cryp->payload_in < AES_BLOCK_SIZE) &&
1599 (stm32_cryp_get_hw_mode(cryp) == CR_AES_CCM) &&
1600 is_decrypt(cryp))) {
1602 if (cryp->caps->padding_wa) {
1604 stm32_cryp_irq_write_ccm_padded_data(cryp);
1609 stm32_cryp_irq_set_npblb(cryp);
1612 if (is_aes(cryp) && is_ctr(cryp))
1613 stm32_cryp_check_ctr_counter(cryp);
1615 stm32_cryp_irq_write_block(cryp);
1618 static void stm32_cryp_irq_write_gcmccm_header(struct stm32_cryp *cryp)
1623 written = min_t(size_t, AES_BLOCK_SIZE, cryp->header_in);
1625 scatterwalk_copychunks(block, &cryp->in_walk, written, 0);
1627 writesl(cryp->regs + cryp->caps->din, block, AES_BLOCK_32);
1629 cryp->header_in -= written;
1631 stm32_crypt_gcmccm_end_header(cryp);
1636 struct stm32_cryp *cryp = arg;
1638 u32 it_mask = stm32_cryp_read(cryp, cryp->caps->imsc);
1640 if (cryp->irq_status & MISR_OUT)
1642 stm32_cryp_irq_read_data(cryp);
1644 if (cryp->irq_status & MISR_IN) {
1645 if (is_gcm(cryp) || is_ccm(cryp)) {
1646 ph = stm32_cryp_read(cryp, cryp->caps->cr) & CR_PH_MASK;
1649 stm32_cryp_irq_write_gcmccm_header(cryp);
1652 stm32_cryp_irq_write_data(cryp);
1653 if (is_gcm(cryp))
1654 cryp->gcm_ctr++;
1657 stm32_cryp_irq_write_data(cryp);
1662 if (!cryp->payload_in && !cryp->header_in)
1664 if (!cryp->payload_out)
1666 stm32_cryp_write(cryp, cryp->caps->imsc, it_mask);
1668 if (!cryp->payload_in && !cryp->header_in && !cryp->payload_out)
1669 stm32_cryp_finish_req(cryp, 0);
1676 struct stm32_cryp *cryp = arg;
1678 cryp->irq_status = stm32_cryp_read(cryp, cryp->caps->mis);
1960 { .compatible = "stericsson,ux500-cryp", .data = &ux500_data},
1961 { .compatible = "st,stm32f756-cryp", .data = &f7_data},
1962 { .compatible = "st,stm32mp1-cryp", .data = &mp1_data},
1970 struct stm32_cryp *cryp;
1974 cryp = devm_kzalloc(dev, sizeof(*cryp), GFP_KERNEL);
1975 if (!cryp)
1978 cryp->caps = of_device_get_match_data(dev);
1979 if (!cryp->caps)
1982 cryp->dev = dev;
1984 cryp->regs = devm_platform_ioremap_resource(pdev, 0);
1985 if (IS_ERR(cryp->regs))
1986 return PTR_ERR(cryp->regs);
1994 dev_name(dev), cryp);
2000 cryp->clk = devm_clk_get(dev, NULL);
2001 if (IS_ERR(cryp->clk)) {
2002 dev_err_probe(dev, PTR_ERR(cryp->clk), "Could not get clock\n");
2004 return PTR_ERR(cryp->clk);
2007 ret = clk_prepare_enable(cryp->clk);
2009 dev_err(cryp->dev, "Failed to enable clock\n");
2031 platform_set_drvdata(pdev, cryp);
2034 list_add(&cryp->list, &cryp_list.dev_list);
2038 cryp->engine = crypto_engine_alloc_init(dev, 1);
2039 if (!cryp->engine) {
2045 ret = crypto_engine_start(cryp->engine);
2057 if (cryp->caps->aeads_support) {
2073 crypto_engine_exit(cryp->engine);
2076 list_del(&cryp->list);
2082 clk_disable_unprepare(cryp->clk);
2089 struct stm32_cryp *cryp = platform_get_drvdata(pdev);
2092 ret = pm_runtime_get_sync(cryp->dev);
2094 if (cryp->caps->aeads_support)
2098 crypto_engine_exit(cryp->engine);
2101 list_del(&cryp->list);
2104 pm_runtime_disable(cryp->dev);
2105 pm_runtime_put_noidle(cryp->dev);
2108 clk_disable_unprepare(cryp->clk);
2114 struct stm32_cryp *cryp = dev_get_drvdata(dev);
2116 clk_disable_unprepare(cryp->clk);
2123 struct stm32_cryp *cryp = dev_get_drvdata(dev);
2126 ret = clk_prepare_enable(cryp->clk);
2128 dev_err(cryp->dev, "Failed to prepare_enable clock\n");