drivers/crypto/s5p-sss.c

211  * HASH bit numbers, used by device, setting in dev->hash_flags with
268  *		in device.  This is DMA-mapped into device.
270  *		in device. This is DMA-mapped into device.
341  * @engine:	Bits for selecting type of HASH in SSS block
345  * @skip:	Skip offset in req->src for current op
349  * @bufcnt:	Number of bytes holded in buffer[]
350  * @buffer:	For byte(s) from end of req->src in UPDATE op
675 	 * If there is no more data in tx scatter list, call s5p_aes_complete()
915  * s5p_hash_write_ctrl() - prepare HASH block in SecSS for processing
920  * Prepare SSS HASH block for processing bytes in DMA mode. If it is called
1017  * Set bit in dd->hash_flag so we can free it after irq ends processing.
1052  * s5p_hash_copy_sg_lists() - copy sg list and make fixes in copy
1126  * Check two conditions: (1) if buffers in sg have len aligned data, and (2)
1129  * data into this buffer and prepare request in sgl, or (2) allocates new sg
1255 		/* previous bytes are in xmit_buf, so no overwrite */
1429 		 * in queue.
1496  * If request will fit in buffer, copy it and return immediately
1522  * Note: in final req->src do not have any data, and req->nbytes can be
1530  * and finalize hash message in HW. Note that if digcnt!=0 then there were
1531  * previous update op, so there are always some buffered bytes in ctx->buffer,
1705  * @in:		buffer with state to be imported from
1707 static int s5p_hash_import(struct ahash_request *req, const void *in)
1712 	const struct s5p_hash_reqctx *ctx_in = in;
1714 	memcpy(ctx, in, sizeof(*ctx) + BUFLEN);
2171 	 * Note: HASH and PRNG uses the same registers in secss, avoid
2173 	 * is enabled in config. We need larger size for HASH registers in