crypto/qce/common.c

21 static inline u32 qce_read(struct qce_device *qce, u32 offset)
23 	return readl(qce->base + offset);
26 static inline void qce_write(struct qce_device *qce, u32 offset, u32 val)
28 	writel(val, qce->base + offset);
31 static inline void qce_write_array(struct qce_device *qce, u32 offset,
37 		qce_write(qce, offset + i * sizeof(u32), val[i]);
41 qce_clear_array(struct qce_device *qce, u32 offset, unsigned int len)
46 		qce_write(qce, offset + i * sizeof(u32), 0);
49 static u32 qce_config_reg(struct qce_device *qce, int little)
51 	u32 beats = (qce->burst_size >> 3) - 1;
52 	u32 pipe_pair = qce->pipe_pair_id;
81 static void qce_setup_config(struct qce_device *qce)
86 	config = qce_config_reg(qce, 0);
89 	qce_write(qce, REG_STATUS, 0);
90 	qce_write(qce, REG_CONFIG, config);
93 static inline void qce_crypto_go(struct qce_device *qce, bool result_dump)
96 		qce_write(qce, REG_GOPROC, BIT(GO_SHIFT) | BIT(RESULTS_DUMP_SHIFT));
98 		qce_write(qce, REG_GOPROC, BIT(GO_SHIFT));
153 	struct qce_device *qce = tmpl->qce;
165 	qce_setup_config(qce);
168 		qce_write(qce, REG_AUTH_SEG_CFG, 0);
169 		qce_write(qce, REG_ENCR_SEG_CFG, 0);
170 		qce_write(qce, REG_ENCR_SEG_SIZE, 0);
171 		qce_clear_array(qce, REG_AUTH_IV0, 16);
172 		qce_clear_array(qce, REG_AUTH_KEY0, 16);
173 		qce_clear_array(qce, REG_AUTH_BYTECNT0, 4);
182 		qce_write_array(qce, REG_AUTH_KEY0, (u32 *)mackey,
195 	qce_write_array(qce, REG_AUTH_IV0, (u32 *)auth, iv_words);
198 		qce_clear_array(qce, REG_AUTH_BYTECNT0, 4);
200 		qce_write_array(qce, REG_AUTH_BYTECNT0,
216 	qce_write(qce, REG_AUTH_SEG_CFG, auth_cfg);
217 	qce_write(qce, REG_AUTH_SEG_SIZE, req->nbytes);
218 	qce_write(qce, REG_AUTH_SEG_START, 0);
219 	qce_write(qce, REG_ENCR_SEG_CFG, 0);
220 	qce_write(qce, REG_SEG_SIZE, req->nbytes);
223 	config = qce_config_reg(qce, 1);
224 	qce_write(qce, REG_CONFIG, config);
226 	qce_crypto_go(qce, true);
298 static void qce_xtskey(struct qce_device *qce, const u8 *enckey,
306 	qce_write_array(qce, REG_ENCR_XTS_KEY0, xtskey, xtsklen);
311 	qce_write(qce, REG_ENCR_XTS_DU_SIZE, cryptlen);
320 	struct qce_device *qce = tmpl->qce;
329 	qce_setup_config(qce);
339 	qce_write(qce, REG_AUTH_SEG_CFG, auth_cfg);
351 			qce_xtskey(qce, ctx->enc_key, ctx->enc_keylen,
358 	qce_write_array(qce, REG_ENCR_KEY0, (u32 *)enckey, enckey_words);
366 		qce_write_array(qce, REG_CNTR0_IV0, (u32 *)enciv, enciv_words);
372 	qce_write(qce, REG_ENCR_SEG_CFG, encr_cfg);
373 	qce_write(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen);
374 	qce_write(qce, REG_ENCR_SEG_START, 0);
377 		qce_write(qce, REG_CNTR_MASK, ~0);
378 		qce_write(qce, REG_CNTR_MASK0, ~0);
379 		qce_write(qce, REG_CNTR_MASK1, ~0);
380 		qce_write(qce, REG_CNTR_MASK2, ~0);
383 	qce_write(qce, REG_SEG_SIZE, rctx->cryptlen);
386 	config = qce_config_reg(qce, 1);
387 	qce_write(qce, REG_CONFIG, config);
389 	qce_crypto_go(qce, true);
426 	struct qce_device *qce = tmpl->qce;
442 	qce_setup_config(qce);
446 	qce_write_array(qce, REG_ENCR_KEY0, enckey, enckey_words);
450 	qce_write_array(qce, REG_CNTR0_IV0, enciv, enciv_words);
454 		qce_write(qce, REG_CNTR3_IV3, iv_last_word + 1);
455 		qce_write_array(qce, REG_ENCR_CCM_INT_CNTR0, (u32 *)enciv, enciv_words);
456 		qce_write(qce, REG_CNTR_MASK, ~0);
457 		qce_write(qce, REG_CNTR_MASK0, ~0);
458 		qce_write(qce, REG_CNTR_MASK1, ~0);
459 		qce_write(qce, REG_CNTR_MASK2, ~0);
463 	qce_clear_array(qce, REG_AUTH_IV0, 16);
464 	qce_clear_array(qce, REG_AUTH_KEY0, 16);
467 	qce_clear_array(qce, REG_AUTH_BYTECNT0, 4);
471 	qce_write_array(qce, REG_AUTH_KEY0, (u32 *)authkey, authkey_words);
484 		qce_write_array(qce, REG_AUTH_IV0, (u32 *)authiv, authiv_words);
488 		qce_write_array(qce, REG_AUTH_INFO_NONCE0, authnonce, authnonce_words);
495 	qce_write(qce, REG_ENCR_SEG_CFG, encr_cfg);
512 	qce_write(qce, REG_AUTH_SEG_CFG, auth_cfg);
518 		qce_write(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen + ctx->authsize);
520 		qce_write(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen);
521 	qce_write(qce, REG_ENCR_SEG_START, rctx->assoclen & 0xffff);
524 	qce_write(qce, REG_AUTH_SEG_SIZE, totallen);
525 	qce_write(qce, REG_AUTH_SEG_START, 0);
529 		qce_write(qce, REG_SEG_SIZE, totallen + ctx->authsize);
531 		qce_write(qce, REG_SEG_SIZE, totallen);
534 	config = qce_config_reg(qce, 1);
535 	qce_write(qce, REG_CONFIG, config);
538 	qce_crypto_go(qce, !IS_CCM(flags));
567 int qce_check_status(struct qce_device *qce, u32 *status)
571 	*status = qce_read(qce, REG_STATUS);
587 void qce_get_version(struct qce_device *qce, u32 *major, u32 *minor, u32 *step)
591 	val = qce_read(qce, REG_VERSION);