marvell/octeontx2/otx2_cptpf_ucode.c

160 static int __write_ucode_base(struct otx2_cptpf_dev *cptpf, int eng,
163 	return otx2_cpt_write_af_reg(&cptpf->afpf_mbox, cptpf->pdev,
169 			       struct otx2_cptpf_dev *cptpf, int blkaddr)
176 	ret = otx2_cpt_write_af_reg(&cptpf->afpf_mbox, cptpf->pdev,
178 				    cptpf->pf_id << RVU_PFVF_PF_SHIFT, blkaddr);
195 				ret = __write_ucode_base(cptpf, bit, dma_addr,
206 	struct otx2_cptpf_dev *cptpf = obj;
209 	if (cptpf->has_cpt1) {
210 		ret = cptx_set_ucode_base(eng_grp, cptpf, BLKADDR_CPT1);
214 	return cptx_set_ucode_base(eng_grp, cptpf, BLKADDR_CPT0);
218 					 struct otx2_cptpf_dev *cptpf,
228 		ret = otx2_cpt_read_af_reg(&cptpf->afpf_mbox, cptpf->pdev,
237 			ret = otx2_cpt_write_af_reg(&cptpf->afpf_mbox,
238 						    cptpf->pdev,
254 			ret = otx2_cpt_read_af_reg(&cptpf->afpf_mbox,
255 						   cptpf->pdev,
271 			ret = otx2_cpt_write_af_reg(&cptpf->afpf_mbox,
272 						    cptpf->pdev,
286 	struct otx2_cptpf_dev *cptpf = obj;
290 	bmap = get_cores_bmap(&cptpf->pdev->dev, eng_grp);
294 	if (cptpf->has_cpt1) {
295 		ret = cptx_detach_and_disable_cores(eng_grp, cptpf, bmap,
300 	return cptx_detach_and_disable_cores(eng_grp, cptpf, bmap,
305 					struct otx2_cptpf_dev *cptpf,
314 		ret = otx2_cpt_read_af_reg(&cptpf->afpf_mbox, cptpf->pdev,
323 			ret = otx2_cpt_write_af_reg(&cptpf->afpf_mbox,
324 						    cptpf->pdev,
334 		ret = otx2_cpt_add_write_af_reg(&cptpf->afpf_mbox, cptpf->pdev,
340 	return otx2_cpt_send_af_reg_requests(&cptpf->afpf_mbox, cptpf->pdev);
346 	struct otx2_cptpf_dev *cptpf = obj;
350 	bmap = get_cores_bmap(&cptpf->pdev->dev, eng_grp);
354 	if (cptpf->has_cpt1) {
355 		ret = cptx_attach_and_enable_cores(eng_grp, cptpf, bmap,
360 	return cptx_attach_and_enable_cores(eng_grp, cptpf, bmap, BLKADDR_CPT0);
1144 int otx2_cpt_create_eng_grps(struct otx2_cptpf_dev *cptpf,
1149 	struct pci_dev *pdev = cptpf->pdev;
1237 	otx2_cpt_read_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_CTL, &reg_val,
1245 	otx2_cpt_write_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_CTL,
1252 	otx2_cpt_write_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_CTX_FLUSH_TIMER,
1262 		otx2_cpt_read_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_DIAG,
1264 		otx2_cpt_write_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_DIAG,
1280 static int cptx_disable_all_cores(struct otx2_cptpf_dev *cptpf, int total_cores,
1289 		ret = otx2_cpt_add_write_af_reg(&cptpf->afpf_mbox, cptpf->pdev,
1295 		cptpf->eng_grps.eng_ref_cnt[i] = 0;
1297 	ret = otx2_cpt_send_af_reg_requests(&cptpf->afpf_mbox, cptpf->pdev);
1309 			ret = otx2_cpt_read_af_reg(&cptpf->afpf_mbox,
1310 						   cptpf->pdev,
1325 		ret = otx2_cpt_add_write_af_reg(&cptpf->afpf_mbox, cptpf->pdev,
1331 	return otx2_cpt_send_af_reg_requests(&cptpf->afpf_mbox, cptpf->pdev);
1334 int otx2_cpt_disable_all_cores(struct otx2_cptpf_dev *cptpf)
1338 	total_cores = cptpf->eng_grps.avail.max_se_cnt +
1339 		      cptpf->eng_grps.avail.max_ie_cnt +
1340 		      cptpf->eng_grps.avail.max_ae_cnt;
1342 	if (cptpf->has_cpt1) {
1343 		ret = cptx_disable_all_cores(cptpf, total_cores, BLKADDR_CPT1);
1347 	return cptx_disable_all_cores(cptpf, total_cores, BLKADDR_CPT0);
1486 int otx2_cpt_discover_eng_capabilities(struct otx2_cptpf_dev *cptpf)
1488 	struct otx2_cptlfs_info *lfs = &cptpf->lfs;
1503 	if (cptpf->is_eng_caps_discovered)
1506 	pdev = cptpf->pdev;
1511 	ret = create_eng_caps_discovery_grps(pdev, &cptpf->eng_grps);
1515 	otx2_cptlf_set_dev_info(lfs, cptpf->pdev, cptpf->reg_base,
1516 				&cptpf->afpf_mbox, BLKADDR_CPT0);
1554 		iq_cmd.cptr.s.grp = otx2_cpt_get_eng_grp(&cptpf->eng_grps,
1557 		lfs->ops->send_cmd(&inst, 1, &cptpf->lfs.lf[0]);
1563 		cptpf->eng_caps[etype].u = be64_to_cpup(rptr);
1566 	cptpf->is_eng_caps_discovered = true;
1573 	delete_engine_grps(pdev, &cptpf->eng_grps);
1578 int otx2_cpt_dl_custom_egrp_create(struct otx2_cptpf_dev *cptpf,
1583 	struct otx2_cpt_eng_grps *eng_grps = &cptpf->eng_grps;
1586 	struct device *dev = &cptpf->pdev->dev;
1691 	if (cptpf->enabled_vfs) {
1740 int otx2_cpt_dl_custom_egrp_delete(struct otx2_cptpf_dev *cptpf,
1743 	struct otx2_cpt_eng_grps *eng_grps = &cptpf->eng_grps;
1744 	struct device *dev = &cptpf->pdev->dev;
1819 void otx2_cpt_print_uc_dbg_info(struct otx2_cptpf_dev *cptpf)
1821 	struct otx2_cpt_eng_grps *eng_grps = &cptpf->eng_grps;
1864 				if (is_dev_otx2(cptpf->pdev))