Lines Matching refs:cptpf
20 static void cptpf_enable_vfpf_mbox_intr(struct otx2_cptpf_dev *cptpf,
26 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
28 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
33 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
40 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
46 static void cptpf_disable_vfpf_mbox_intr(struct otx2_cptpf_dev *cptpf,
52 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
54 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
57 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
60 vector = pci_irq_vector(cptpf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0);
61 free_irq(vector, cptpf);
64 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
66 vector = pci_irq_vector(cptpf->pdev, RVU_PF_INT_VEC_VFPF_MBOX1);
67 free_irq(vector, cptpf);
71 static void cptpf_enable_vf_flr_me_intrs(struct otx2_cptpf_dev *cptpf,
75 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, RVU_PF_VFFLR_INTX(0),
79 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
82 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, RVU_PF_VFME_INTX(0),
85 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
91 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, RVU_PF_VFFLR_INTX(1),
93 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
96 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, RVU_PF_VFME_INTX(1),
98 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
102 static void cptpf_disable_vf_flr_me_intrs(struct otx2_cptpf_dev *cptpf,
108 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
110 vector = pci_irq_vector(cptpf->pdev, RVU_PF_INT_VEC_VFFLR0);
111 free_irq(vector, cptpf);
114 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
116 vector = pci_irq_vector(cptpf->pdev, RVU_PF_INT_VEC_VFME0);
117 free_irq(vector, cptpf);
122 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
124 vector = pci_irq_vector(cptpf->pdev, RVU_PF_INT_VEC_VFFLR1);
125 free_irq(vector, cptpf);
127 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
129 vector = pci_irq_vector(cptpf->pdev, RVU_PF_INT_VEC_VFME1);
130 free_irq(vector, cptpf);
179 struct otx2_cptpf_dev *cptpf = arg;
182 if (cptpf->max_vfs > 64)
186 intr = otx2_cpt_read64(cptpf->reg_base, BLKADDR_RVUM, 0,
195 queue_work(cptpf->flr_wq, &cptpf->flr_work[dev].work);
197 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
200 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
210 struct otx2_cptpf_dev *cptpf = arg;
214 if (cptpf->max_vfs > 64)
218 intr = otx2_cpt_read64(cptpf->reg_base, BLKADDR_RVUM, 0,
225 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
228 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0,
235 static void cptpf_unregister_vfpf_intr(struct otx2_cptpf_dev *cptpf,
238 cptpf_disable_vfpf_mbox_intr(cptpf, num_vfs);
239 cptpf_disable_vf_flr_me_intrs(cptpf, num_vfs);
242 static int cptpf_register_vfpf_intr(struct otx2_cptpf_dev *cptpf, int num_vfs)
244 struct pci_dev *pdev = cptpf->pdev;
251 cptpf);
259 ret = request_irq(vector, cptpf_vf_flr_intr, 0, "CPTPF FLR0", cptpf);
267 ret = request_irq(vector, cptpf_vf_me_intr, 0, "CPTPF ME0", cptpf);
277 "CPTVFPF Mbox1", cptpf);
286 cptpf);
295 cptpf);
302 cptpf_enable_vfpf_mbox_intr(cptpf, num_vfs);
303 cptpf_enable_vf_flr_me_intrs(cptpf, num_vfs);
309 free_irq(vector, cptpf);
312 free_irq(vector, cptpf);
315 free_irq(vector, cptpf);
318 free_irq(vector, cptpf);
321 free_irq(vector, cptpf);
334 static int cptpf_flr_wq_init(struct otx2_cptpf_dev *cptpf, int num_vfs)
338 cptpf->flr_wq = alloc_ordered_workqueue("cptpf_flr_wq", 0);
339 if (!cptpf->flr_wq)
342 cptpf->flr_work = kcalloc(num_vfs, sizeof(struct cptpf_flr_work),
344 if (!cptpf->flr_work)
348 cptpf->flr_work[vf].pf = cptpf;
349 INIT_WORK(&cptpf->flr_work[vf].work, cptpf_flr_wq_handler);
354 destroy_workqueue(cptpf->flr_wq);
358 static int cptpf_vfpf_mbox_init(struct otx2_cptpf_dev *cptpf, int num_vfs)
360 struct device *dev = &cptpf->pdev->dev;
364 cptpf->vfpf_mbox_wq =
367 if (!cptpf->vfpf_mbox_wq)
371 if (test_bit(CN10K_MBOX, &cptpf->cap_flag))
372 vfpf_mbox_base = readq(cptpf->reg_base + RVU_PF_VF_MBOX_ADDR);
374 vfpf_mbox_base = readq(cptpf->reg_base + RVU_PF_VF_BAR4_ADDR);
381 cptpf->vfpf_mbox_base = devm_ioremap_wc(dev, vfpf_mbox_base,
382 MBOX_SIZE * cptpf->max_vfs);
383 if (!cptpf->vfpf_mbox_base) {
388 err = otx2_mbox_init(&cptpf->vfpf_mbox, cptpf->vfpf_mbox_base,
389 cptpf->pdev, cptpf->reg_base, MBOX_DIR_PFVF,
395 cptpf->vf[i].vf_id = i;
396 cptpf->vf[i].cptpf = cptpf;
397 cptpf->vf[i].intr_idx = i % 64;
398 INIT_WORK(&cptpf->vf[i].vfpf_mbox_work,
404 destroy_workqueue(cptpf->vfpf_mbox_wq);
408 static void cptpf_vfpf_mbox_destroy(struct otx2_cptpf_dev *cptpf)
410 destroy_workqueue(cptpf->vfpf_mbox_wq);
411 otx2_mbox_destroy(&cptpf->vfpf_mbox);
414 static void cptpf_disable_afpf_mbox_intr(struct otx2_cptpf_dev *cptpf)
417 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, RVU_PF_INT_ENA_W1C,
420 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, RVU_PF_INT, 0x1ULL);
423 static int cptpf_register_afpf_mbox_intr(struct otx2_cptpf_dev *cptpf)
425 struct pci_dev *pdev = cptpf->pdev;
432 "CPTAFPF Mbox", cptpf);
439 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, RVU_PF_INT, 0x1ULL);
441 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, RVU_PF_INT_ENA_W1S,
444 ret = otx2_cpt_send_ready_msg(&cptpf->afpf_mbox, cptpf->pdev);
448 cptpf_disable_afpf_mbox_intr(cptpf);
454 static int cptpf_afpf_mbox_init(struct otx2_cptpf_dev *cptpf)
456 struct pci_dev *pdev = cptpf->pdev;
460 cptpf->afpf_mbox_wq =
463 if (!cptpf->afpf_mbox_wq)
468 cptpf->afpf_mbox_base = devm_ioremap_wc(&pdev->dev, offset, MBOX_SIZE);
469 if (!cptpf->afpf_mbox_base) {
475 err = otx2_mbox_init(&cptpf->afpf_mbox, cptpf->afpf_mbox_base,
476 pdev, cptpf->reg_base, MBOX_DIR_PFAF, 1);
480 err = otx2_mbox_init(&cptpf->afpf_mbox_up, cptpf->afpf_mbox_base,
481 pdev, cptpf->reg_base, MBOX_DIR_PFAF_UP, 1);
485 INIT_WORK(&cptpf->afpf_mbox_work, otx2_cptpf_afpf_mbox_handler);
486 INIT_WORK(&cptpf->afpf_mbox_up_work, otx2_cptpf_afpf_mbox_up_handler);
487 mutex_init(&cptpf->lock);
492 otx2_mbox_destroy(&cptpf->afpf_mbox);
494 destroy_workqueue(cptpf->afpf_mbox_wq);
498 static void cptpf_afpf_mbox_destroy(struct otx2_cptpf_dev *cptpf)
500 destroy_workqueue(cptpf->afpf_mbox_wq);
501 otx2_mbox_destroy(&cptpf->afpf_mbox);
502 otx2_mbox_destroy(&cptpf->afpf_mbox_up);
508 struct otx2_cptpf_dev *cptpf = dev_get_drvdata(dev);
510 return sprintf(buf, "%d\n", cptpf->sso_pf_func_ovrd);
517 struct otx2_cptpf_dev *cptpf = dev_get_drvdata(dev);
520 if (!(cptpf->pdev->revision == CPT_UC_RID_CN9K_B0))
526 cptpf->sso_pf_func_ovrd = sso_pf_func_ovrd;
534 struct otx2_cptpf_dev *cptpf = dev_get_drvdata(dev);
536 return sprintf(buf, "%d\n", cptpf->kvf_limits);
543 struct otx2_cptpf_dev *cptpf = dev_get_drvdata(dev);
555 cptpf->kvf_limits = lfs_num;
573 static int cpt_is_pf_usable(struct otx2_cptpf_dev *cptpf)
577 rev = otx2_cpt_read64(cptpf->reg_base, BLKADDR_RVUM, 0,
585 dev_warn(&cptpf->pdev->dev,
592 static void cptpf_get_rid(struct pci_dev *pdev, struct otx2_cptpf_dev *cptpf)
594 struct otx2_cpt_eng_grps *eng_grps = &cptpf->eng_grps;
601 otx2_cpt_read_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_CTL, ®_val,
610 static void cptpf_check_block_implemented(struct otx2_cptpf_dev *cptpf)
614 cfg = otx2_cpt_read64(cptpf->reg_base, BLKADDR_RVUM, 0,
617 cptpf->has_cpt1 = true;
620 static int cptpf_device_init(struct otx2_cptpf_dev *cptpf)
626 cptpf_check_block_implemented(cptpf);
629 ret = otx2_cpt_read_af_reg(&cptpf->afpf_mbox, cptpf->pdev,
635 cptpf->eng_grps.avail.max_se_cnt = af_cnsts1.s.se;
636 cptpf->eng_grps.avail.max_ie_cnt = af_cnsts1.s.ie;
637 cptpf->eng_grps.avail.max_ae_cnt = af_cnsts1.s.ae;
640 ret = otx2_cpt_disable_all_cores(cptpf);
647 struct otx2_cptpf_dev *cptpf = pci_get_drvdata(pdev);
654 cptpf_unregister_vfpf_intr(cptpf, num_vfs);
655 cptpf_flr_wq_destroy(cptpf);
656 cptpf_vfpf_mbox_destroy(cptpf);
658 cptpf->enabled_vfs = 0;
665 struct otx2_cptpf_dev *cptpf = pci_get_drvdata(pdev);
669 ret = cptpf_vfpf_mbox_init(cptpf, num_vfs);
673 ret = cptpf_flr_wq_init(cptpf, num_vfs);
677 ret = cptpf_register_vfpf_intr(cptpf, num_vfs);
681 cptpf_get_rid(pdev, cptpf);
683 ret = otx2_cpt_discover_eng_capabilities(cptpf);
687 ret = otx2_cpt_create_eng_grps(cptpf, &cptpf->eng_grps);
691 cptpf->enabled_vfs = num_vfs;
696 dev_notice(&cptpf->pdev->dev, "VFs enabled: %d\n", num_vfs);
702 cptpf_unregister_vfpf_intr(cptpf, num_vfs);
703 cptpf->enabled_vfs = 0;
705 cptpf_flr_wq_destroy(cptpf);
707 cptpf_vfpf_mbox_destroy(cptpf);
724 struct otx2_cptpf_dev *cptpf;
727 cptpf = devm_kzalloc(dev, sizeof(*cptpf), GFP_KERNEL);
728 if (!cptpf)
750 pci_set_drvdata(pdev, cptpf);
751 cptpf->pdev = pdev;
753 cptpf->reg_base = pcim_iomap_table(pdev)[PCI_PF_REG_BAR_NUM];
756 err = cpt_is_pf_usable(cptpf);
760 num_vec = pci_msix_vec_count(cptpf->pdev);
772 otx2_cpt_set_hw_caps(pdev, &cptpf->cap_flag);
774 err = cptpf_afpf_mbox_init(cptpf);
778 err = cptpf_register_afpf_mbox_intr(cptpf);
782 cptpf->max_vfs = pci_sriov_get_totalvfs(pdev);
783 cptpf->kvf_limits = 1;
785 err = cn10k_cptpf_lmtst_init(cptpf);
790 err = cptpf_device_init(cptpf);
795 err = otx2_cpt_init_eng_grps(pdev, &cptpf->eng_grps);
803 err = otx2_cpt_register_dl(cptpf);
812 otx2_cpt_cleanup_eng_grps(pdev, &cptpf->eng_grps);
814 cptpf_disable_afpf_mbox_intr(cptpf);
816 cptpf_afpf_mbox_destroy(cptpf);
824 struct otx2_cptpf_dev *cptpf = pci_get_drvdata(pdev);
826 if (!cptpf)
830 otx2_cpt_unregister_dl(cptpf);
833 if (cptpf->lfs.lfs_num)
834 otx2_inline_cptlf_cleanup(&cptpf->lfs);
836 if (cptpf->cpt1_lfs.lfs_num)
837 otx2_inline_cptlf_cleanup(&cptpf->cpt1_lfs);
842 otx2_cpt_cleanup_eng_grps(pdev, &cptpf->eng_grps);
844 cptpf_disable_afpf_mbox_intr(cptpf);
846 cptpf_afpf_mbox_destroy(cptpf);