marvell/octeontx2/otx2_cptlf.c

11 static void cptlf_do_set_done_time_wait(struct otx2_cptlf_info *lf,
16 	done_wait.u = otx2_cpt_read64(lf->lfs->reg_base, lf->lfs->blkaddr,
17 				      lf->slot, OTX2_CPT_LF_DONE_WAIT);
19 	otx2_cpt_write64(lf->lfs->reg_base, lf->lfs->blkaddr, lf->slot,
23 static void cptlf_do_set_done_num_wait(struct otx2_cptlf_info *lf, int num_wait)
27 	done_wait.u = otx2_cpt_read64(lf->lfs->reg_base, lf->lfs->blkaddr,
28 				      lf->slot, OTX2_CPT_LF_DONE_WAIT);
30 	otx2_cpt_write64(lf->lfs->reg_base, lf->lfs->blkaddr, lf->slot,
40 		cptlf_do_set_done_time_wait(&lfs->lf[slot], time_wait);
48 		cptlf_do_set_done_num_wait(&lfs->lf[slot], num_wait);
51 static int cptlf_set_pri(struct otx2_cptlf_info *lf, int pri)
53 	struct otx2_cptlfs_info *lfs = lf->lfs;
58 				   CPT_AF_LFX_CTL(lf->slot),
66 				    CPT_AF_LFX_CTL(lf->slot),
71 static int cptlf_set_eng_grps_mask(struct otx2_cptlf_info *lf,
74 	struct otx2_cptlfs_info *lfs = lf->lfs;
79 				   CPT_AF_LFX_CTL(lf->slot),
87 				    CPT_AF_LFX_CTL(lf->slot),
98 		ret = cptlf_set_pri(&lfs->lf[slot], pri);
102 		ret = cptlf_set_eng_grps_mask(&lfs->lf[slot], eng_grp_mask);
112 	struct otx2_cptlf_info *lf;
116 		lf = &lfs->lf[slot];
119 					   CPT_AF_LFX_CTL(lf->slot),
127 					    CPT_AF_LFX_CTL(lf->slot),
190 static inline int cptlf_read_done_cnt(struct otx2_cptlf_info *lf)
194 	irq_cnt.u = otx2_cpt_read64(lf->lfs->reg_base, lf->lfs->blkaddr, lf->slot,
202 	struct otx2_cptlf_info *lf = arg;
205 	dev = &lf->lfs->pdev->dev;
206 	irq_misc.u = otx2_cpt_read64(lf->lfs->reg_base, lf->lfs->blkaddr,
207 				     lf->slot, OTX2_CPT_LF_MISC_INT);
212 			lf->slot);
217 			lf->slot);
222 			lf->slot);
234 		dev_err(dev, "Unhandled interrupt in CPT LF %d\n", lf->slot);
239 	otx2_cpt_write64(lf->lfs->reg_base, lf->lfs->blkaddr, lf->slot,
248 	struct otx2_cptlf_info *lf = arg;
252 	irq_cnt = cptlf_read_done_cnt(lf);
254 		done_wait.u = otx2_cpt_read64(lf->lfs->reg_base, lf->lfs->blkaddr,
255 					      lf->slot, OTX2_CPT_LF_DONE_WAIT);
257 		otx2_cpt_write64(lf->lfs->reg_base, lf->lfs->blkaddr, lf->slot,
260 		otx2_cpt_write64(lf->lfs->reg_base, lf->lfs->blkaddr, lf->slot,
262 		if (unlikely(!lf->wqe)) {
263 			dev_err(&lf->lfs->pdev->dev, "No work for LF %d\n",
264 				lf->slot);
269 		tasklet_hi_schedule(&lf->wqe->work);
280 		if (!lfs->lf[i].is_irq_reg[irq_offs])
284 					lfs->lf[i].msix_offset + irq_offs);
285 		free_irq(vector, &lfs->lf[i]);
286 		lfs->lf[i].is_irq_reg[irq_offs] = false;
300 		if (!lfs->lf[i].is_irq_reg[irq_offs])
304 					lfs->lf[i].msix_offset + irq_offs);
305 		free_irq(vector, &lfs->lf[i]);
306 		lfs->lf[i].is_irq_reg[irq_offs] = false;
320 	vector = pci_irq_vector(lfs->pdev, lfs->lf[lf_num].msix_offset +
323 			  lfs->lf[lf_num].irq_name[irq_offset],
324 			  &lfs->lf[lf_num]);
328 	lfs->lf[lf_num].is_irq_reg[irq_offset] = true;
340 		snprintf(lfs->lf[i].irq_name[irq_offs], 32, "CPT%dLF Misc%d",
364 		snprintf(lfs->lf[i].irq_name[irq_offs], 32,
388 					      lfs->lf[slot].msix_offset +
390 		free_cpumask_var(lfs->lf[slot].affinity_mask);
397 	struct otx2_cptlf_info *lf = lfs->lf;
401 		if (!zalloc_cpumask_var(&lf[slot].affinity_mask, GFP_KERNEL)) {
410 				lf[slot].affinity_mask);
414 						lf[slot].msix_offset + offs),
415 						lf[slot].affinity_mask);
438 		lfs->lf[slot].lfs = lfs;
439 		lfs->lf[slot].slot = slot;
441 			lfs->lf[slot].lmtline = lfs->lmt_base +
444 			lfs->lf[slot].lmtline = lfs->reg_base +
448 		lfs->lf[slot].ioreg = lfs->reg_base +