Lines Matching refs:bank
76 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \
78 ADF_RING_BUNDLE_SIZE * (bank) + \
80 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \
82 ADF_RING_BUNDLE_SIZE * (bank) + \
84 #define READ_CSR_E_STAT(csr_base_addr, bank) \
86 ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_E_STAT)
87 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \
89 ADF_RING_BUNDLE_SIZE * (bank) + \
91 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \
94 u32 _bank = bank; \
108 #define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \
110 ADF_RING_BUNDLE_SIZE * (bank) + \
112 #define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \
114 ADF_RING_BUNDLE_SIZE * (bank) + \
116 #define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) \
118 ADF_RING_BUNDLE_SIZE * (bank) + \
120 #define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \
122 ADF_RING_BUNDLE_SIZE * (bank) + \
124 #define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \
126 ADF_RING_BUNDLE_SIZE * (bank) + \
128 #define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \
130 ADF_RING_BUNDLE_SIZE * (bank) + \
133 #define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \
135 ADF_RING_BUNDLE_SIZE * (bank) + \
141 #define WRITE_CSR_RING_SRV_ARB_EN(csr_base_addr, bank, value) \
143 ADF_RING_BUNDLE_SIZE * (bank) + \
169 #define ADF_WQM_CSR_RPRESETCTL(bank) (0x6000 + ((bank) << 3))
171 #define ADF_WQM_CSR_RPRESETSTS(bank) (ADF_WQM_CSR_RPRESETCTL(bank) + 4)