Lines Matching refs:bank
31 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \
32 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
34 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \
35 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
37 #define READ_CSR_E_STAT(csr_base_addr, bank) \
38 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
40 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \
41 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
43 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \
48 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
50 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
54 #define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \
55 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
57 #define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \
58 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
60 #define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) \
61 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
63 #define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \
65 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
67 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
70 #define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \
71 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
73 #define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \
74 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
77 #define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \
78 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \